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5962-9319502MYA

更新时间： 2024-01-06 19:13:11
品牌 Logo 应用领域
美国国家半导体 - NSC 模拟IC信号电路
页数 文件大小 规格书
43页 993K
描述
12-Bit Sign Data Acquisition System with Self-Calibration

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5962-9319502MYA 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：QFP,针数：44
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：S-CQFP-G44JESD-609代码：e0
长度：14.985 mm功能数量：1
端子数量：44最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QFP封装形状：SQUARE
封装形式：FLATPACK认证状态：Not Qualified
筛选级别：MIL-STD-883座面最大高度：4.37 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
温度等级：MILITARY端子面层：TIN LEAD
端子形式：GULL WING端子节距：1.27 mm
端子位置：QUAD宽度：14.985 mm
Base Number Matches：1

5962-9319502MYA 数据手册

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Converter Characteristics (Notes 6, 7, 8, 9, 19) (Continued)  
=
=
=
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ VD+ 5V, VREF+ 5V, VREF− 0V,  
=
=
=
12-bit + sign conversion mode, fCLK 8.0 MHz (LM12H458) or fCLK 5.0 MHz (LM12454/8), RS 25Ω, source impedance for  
VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless  
otherwise specified. Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.  
=
=
=
=
Symbol  
Parameter  
Conditions  
Typical  
Limits  
Unit  
(Limit)  
LSB  
(Note 10) (Note 11)  
±
8-Bit + Sign and “Watchdog” Mode  
DC Common Mode Error  
Multiplexer Channel-to-Channel  
Matching  
1/8  
±
0.05  
LSB  
VIN+  
Non-Inverting Input Range  
GND  
VA+  
V (min)  
V (max)  
V (min)  
V (max)  
V (min)  
V (max)  
V (min)  
V (max)  
LSB (max)  
LSB (max)  
LSB  
VIN−  
Inverting Input Range  
GND  
VA+  
+
VIN+ − VIN−  
Differential Input Voltage Range  
Common Mode Input Voltage Range  
−VA  
VA+  
GND  
VA+  
=
=
±
±
±
1.75  
PSS  
Power Supply  
Sensitivity  
Zero Error  
Full-Scale Error  
Linearity Error  
VA+ VD+ 5V 10%  
0.2  
0.4  
0.2  
=
=
±
±
2
VREF+ 4.5V, VREF− GND  
±
(Note 15)  
CREF  
CIN  
VREF+/VREF− Input Capacitance  
Selected Multiplexer Channel Input  
Capacitance  
85  
75  
pF  
pF  
Converter AC Characteristics (Notes 6, 7, 8, 9, 19)  
=
=
=
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ VD+ 5V, VREF+ 5V, VREF− 0V,  
=
=
=
12-bit + sign conversion mode, fCLK 8.0 MHz (LM12H458) or fCLK 5.0 MHz (LM12454/8), RS 25Ω, source impedance for  
VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless  
=
=
=
=
otherwise specified. Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.  
Symbol  
Parameter  
Clock Duty Cycle  
Conditions  
Typical  
(Note 10)  
50  
Limits  
Unit  
(Limit)  
%
(Note 11)  
40  
60  
% (min)  
%
(max)  
tC  
Conversion Time  
Acquisition Time  
13-Bit Resolution,  
44 (tCLK  
)
)
44 (tCLK) + 50 ns  
21 (tCLK) + 50 ns  
9 (tCLK) + 50 ns  
2 (tCLK) + 50 ns  
(max)  
(max)  
(max)  
(max)  
Sequencer State S5 (Figure 15)  
9-Bit Resolution,  
21 (tCLK  
Sequencer State S5 (Figure 15)  
Sequencer State S7 (Figure 15)  
Built-in minimum for 13-Bits  
Built-in minimum for 9-Bits and  
“Watchdog” mode  
tA  
9 (tCLK  
)
2 (tCLK  
)
tZ  
Auto-Zero Time  
Full Calibration Time  
Throughput Rate  
(Note 18)  
Sequencer State S2 (Figure 15)  
Sequencer State S2 (Figure 15)  
76 (tCLK  
)
76 (tCLK) + 50 ns  
4944 (tCLK) + 50 ns  
88  
(max)  
(max)  
kHz  
tCAL  
4944 (tCLK  
)
89  
LM12H458  
142  
140  
(min)  
(max)  
tWD  
“Watchdog” Mode Comparison  
Time  
Sequencer States S6, S4,  
and S5 (Figure 15)  
11 (tCLK  
)
11 (tCLK) + 50 ns  
5
www.national.com  
12345678...43

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