Datasheet > 存储 > FIFO> 5962-9317709VTX

5962-9317709VTX

更新时间： 2024-02-12 03:07:31

品牌	Logo	应用领域
爱特美尔 - ATMEL		先进先出芯片
页数	文件大小	规格书
20页	2117K
描述
FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28

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5962-9317709VTX 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.13
最长访问时间：	30 ns	周期时间：	40 ns
JESD-30 代码：	R-CDIP-T28	长度：	27.94 mm
内存密度：	147456 bit	内存宽度：	9
功能数量：	1	端子数量：	28
字数：	16384 words	字数代码：	16000
工作模式：	ASYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	16KX9
可输出：	NO	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
认证状态：	Not Qualified	筛选级别：	MIL-PRF-38535 Class V
座面最大高度：	3.94 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	7.62 mm	Base Number Matches：	1

5962-9317709VTX 数据手册

Figure 2. Reset (write (read) to Programmable Half Full Flag register)

Write Enable (W)

A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.

Data set-up and hold times must be maintained in the rise time of the leading edge of

the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any

current read operation.

Once half the memory is filled, and during the falling edge of the next write operation,

the Half-Full Flag (HF) will be set to low and remain in this state until the difference

between the write and read pointers is less than or equal to half of the total available

memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the

read operation.

To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-

tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,

allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is

blocked from W, so that external changes to W will have no effect on the full FIFO stack.

Read Enable (R)

A read cycle is initiated on the falling edge of the Read Enable (R) provided that the

Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not including

any current write operations. After Read Enable (R) goes high, the Data Outputs

(Q0 - Q8) will return to a high impedance state until the next Read operation. When all

the data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the

“final” read cycle, but inhibiting further read operations while the data outputs remain in

a high impedance state. Once a valid write operation has been completed, the Empty

Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO

stack is empty, the internal read pointer is blocked from R, so that external changes to R

will have no effect on the empty FIFO stack.

First Load/Retransmit

(FL/RT)

This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to

ground to indicate that it is the first loaded (see Operating Modes). In the Single Device

Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by con-

necting the Expansion In (XI) to ground.

The M672061H can be set to retransmit data when the Retransmit Enable Control (RT)

input is pulsed low. A retransmit operation will set the internal read point to the first loca-

tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be

in the high state during retransmit. The retransmit feature is intended for use when a

number of writes are equal to or less than the depth of the FIFO has occured since the

last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode

and will affect the Half-Full Flag (HF), in accordance with the relative locations of the

read and write pointers.

M672061H

4144K-AERO-04/07

1 2 345 6 7...20

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与5962-9317709VTX相关器件

型号	品牌	描述	获取价格	数据表
5962-9317710QNC	ATMEL	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag	获取价格
5962-9317710QTC	ATMEL	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag	获取价格
5962-9317710VNC	ATMEL	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag	获取价格
5962-9317710VTC	ATMEL	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag	获取价格
5962-9317710VTX	ATMEL	FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28	获取价格
5962-9317801MZX	ETC	Electroluminescent Display Driver	获取价格

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