Datasheet > 5962-9317704VZX

5962-9317704VZX

更新时间： 2024-01-01 12:50:38

品牌	Logo	应用领域
TEMIC		先进先出芯片
页数	文件大小	规格书
32页	194K
描述
FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDFP28,

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技术参数
数据手册

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5962-9317704VZX 技术参数

生命周期：	Obsolete	零件包装代码：	DFP
包装说明：	DFP,	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.12
最长访问时间：	15 ns	周期时间：	25 ns
JESD-30 代码：	R-CDFP-F28	长度：	18.288 mm
内存密度：	147456 bit	内存宽度：	9
功能数量：	1	端子数量：	28
字数：	16384 words	字数代码：	16000
工作模式：	ASYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	16KX9
可输出：	NO	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK	并行/串行：	PARALLEL
认证状态：	Not Qualified	筛选级别：	MIL-PRF-38535 Class V
座面最大高度：	3.3 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	FLAT
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	10.16 mm	Base Number Matches：	1

5962-9317704VZX 数据手册

4.2.1 Additional criteria for device class M.

a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)

electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.

b. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made

available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs,

biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015.

(1) Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).

c. Interim and final electrical parameters shall be as specified in table IIA herein.

4.2.2 Additional criteria for device classes Q and V.

a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the

device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained

under document revision level control of the device manufacturer's Technology Review Board (TRB) in

accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request.

The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with

the intent specified in test method 1015 of MIL-STD-883.

b. Interim and final electrical test parameters shall be as specified in table IIA herein.

c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-

PRF-38535, appendix B.

4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in

accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for

groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).

4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-

PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for

device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be

performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D,

and E inspections (see 4.4.1 through 4.4.4).

4.4.1 Group A inspection.

a. Tests shall be as specified in table IIA herein.

b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted.

c. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and

V, subgroups 7 and 8 shall include verifying the functionality of the device.

d. O/V (Latch up) tests shall be measured only for the initial qualification and after any process or design changes

which may affect the performance of the device. For device class M, procedures and circuits shall be manitained

under document revision level control by the manufacturer and shall be made available to the preparing or

acquiring activity upon request. For device classes Q and V, the procedures and circuit shall be under the

control of the device manufacturer’s TRB in accordance with MIL-PRF-38535 and shall be made available to the

preparing or acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures.

Latch-up test shall be considered destructive. Information contained in JEDEC Standard EIA/JESD78 may be

used for reference.

e. Subgroup 4 (C_INand C_OUTmeasurements) shall be measured only for initial qualification and after any process or

design changes which may affect input or output capacitance. Capacitance shall be measured between the

designated terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input

and output terminals tested.

SIZE

STANDARD

5962-93177

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

REVISION LEVEL

SHEET

DSCC FORM 2234

APR 97

1...3 4 567 8 9...32

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与5962-9317704VZX相关器件

型号	品牌	描述	获取价格	数据表
5962-9317705QNC	MICROCHIP	FIFO, 16KX9, 30ns, Asynchronous, CMOS	获取价格
5962-9317705QTC	MICROCHIP	FIFO, 16KX9, 30ns, Asynchronous, CMOS, DIP-28	获取价格
5962-9317705QZX	WEDC	IC 16K X 9 OTHER FIFO, 30 ns, CDFP28, 0.400 INCH, FP-28, FIFO	获取价格
5962-9317705VNC	ATMEL	FIFO, 16KX9, 30ns, Asynchronous, CMOS, FP-28	获取价格
5962-9317705VUX	TEMIC	FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28	获取价格
5962-9317705VZA	TEMIC	FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDFP28, 0.400 INCH, FP-28	获取价格

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