5秒后页面跳转
捷配首页

Datasheet > 5962-9220504MLA
5962-9220504MLA PDF预览

5962-9220504MLA

更新时间： 2024-02-17 13:03:59
品牌 Logo 应用领域
德州仪器 - TI 外围集成电路输出元件
页数 文件大小 规格书
8页 85K
描述
Multi-Level Pipeline Register

阅读下载

中文翻译

获取价格

5962-9220504MLA 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.14
边界扫描：NO最大时钟频率：12.5 MHz
外部数据总线宽度：8JESD-30 代码：R-GDIP-T24
长度：32.005 mm低功率模式：YES
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出数据总线宽度：8
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Qualified
筛选级别：MIL-PRF-38535座面最大高度：5.08 mm
子类别：DSP Peripherals最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
uPs/uCs/外围集成电路类型：DSP PERIPHERAL, PIPELINE REGISTERBase Number Matches：1

5962-9220504MLA 数据手册

 浏览型号5962-9220504MLA的Datasheet PDF文件第2页浏览型号5962-9220504MLA的Datasheet PDF文件第3页浏览型号5962-9220504MLA的Datasheet PDF文件第4页浏览型号5962-9220504MLA的Datasheet PDF文件第5页浏览型号5962-9220504MLA的Datasheet PDF文件第6页浏览型号5962-9220504MLA的Datasheet PDF文件第7页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY29FCT520T  
SCCS011A - May 1994 - Revised April 2000  
Multi-Level Pipeline Register  
Features  
Functional Description  
• Function, pinout, and drive compatible with FCT, F  
The CY29FCT520T devices are multilevel 8-bit-wide pipeline  
registers. The devices consist of four registers, A1, A2, B1,  
and B2, which are configured by the instruction inputs I0, I1 as  
a single 4-level pipeline or as two two-level pipelines. The  
contents of any register may be read at the multiplexed out-  
put at any time by using the mux-selection controls S0 and  
S1.  
Logic, and AM29520  
• FCT-C speed at 6.0 ns max. (Com’l),  
FCT-B speed at 7.5 ns max. (Com’l),  
FCT-A speed at 14.0 ns max. (Com’l)  
• Reduced VOH (typically = 3.3V) versions of equivalent  
FCT functions  
• Edge-rate control circuitry for significantly improved  
The pipeline registers are positive edge triggered and data is  
shifted by the rising edge of the clock input. Instruction I=0  
selects the four-level pipeline mode. Instruction I=1 selects the  
two-level B pipeline while I=2 selects the two-level A pipeline.  
I=3 is the HOLD instruction; no shifting is performed by the  
clock in this mode.  
noise characteristics  
• Power-Off disable feature  
• Matched rise and fall times  
• Fully compatible with TTL input and output logic levels  
• ESD > 2000V  
In the two-level operation mode, data is shifted from level 1 to  
level 2 and new data is loaded into level 1.  
• Sink current  
Source current  
64 mA (Com’l), 32 mA (Mil)  
32 mA (Com’l), 12 mA (Mil)  
• Single and dual pipeline operation modes  
• Multiplexed data inputs and outputs  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards.  
Logic Block Diagram  
Pin Configurations  
D –D  
0
7
8
DIP, SOIC, QSOP, CDIP  
Top View  
INSTRUCTION  
I
0
MUX  
1
REGISTER  
CONTROLS  
24  
I
V
S
0
CC  
I
1
2
3
4
5
6
I
1
23  
22  
21  
CLOCK  
0
S
1
D
0
D
1
Y
0
OCTAL REG  
OCTAL REG  
B1  
20  
19  
18  
17  
16  
D
2
Y
A1  
1
D
3
Y
2
D
7
4
Y
3
D
5
8
MUX  
SEL  
S
Y
4
0
OCTAL REG  
A2  
OCTAL REG  
B2  
D
6
9
S
1
Y
5
D
10  
11  
12  
Y
7
6
15  
14  
CLK  
Y
7
GND  
13  
OE  
MUX  
OE  
8
Y –Y  
0
7
Pipeline Instruction Table  
I = 0  
I = 1  
I = 2  
I = 3  
I1 = 0  
I0 = 0  
I1 = 0  
I0 = 1  
I1 = 1 I0 = 0  
I1 = 1  
I0 = 1  
A1  
A2  
B1  
B2  
A1  
A2  
B1  
B2  
A1  
A2  
B1  
B2  
A1  
A2  
B1  
B2  
Single four-level  
Dual two-level  
Hold  
Copyright © 2000, Texas Instruments Incorporated  
12345678

中文翻译

下载PDF

5962-9220504MLA 替代型号

型号 品牌 替代类型 描述 数据表
CY29FCT520ATPCE4 TI

类似代替

 Multi-Level Pipeline Register
CY29FCT520BTSOCTE4 TI

类似代替

 Multi-Level Pipeline Register
CY29FCT520ATPC TI

功能相似

 Multi-Level Pipeline Register

与5962-9220504MLA相关器件

型号 品牌 获取价格 描述 数据表
5962-9220506M3A ETC

获取价格

 		Pipeline Register
5962-9220506MKA ETC

获取价格

 		Pipeline Register
5962-9220506MKX WEDC

获取价格

 		IC 8-BIT, DSP-PIPELINE REGISTER, CDFP24, CERPACK-24, DSP Peripheral
5962-9220506MLA ETC

获取价格

 		Pipeline Register
5962-9220506MLX WEDC

获取价格

 		IC 8-BIT, DSP-PIPELINE REGISTER, CDIP24, CERDIP-24, DSP Peripheral
5962-9220601M2A IDT

获取价格

 		LCC-20, Tube
5962-9220601M2X ETC

获取价格

 		8-Input Digital Multiplexer
5962-9220601MEA IDT

获取价格

 		CDIP-16, Tube
5962-9220601MEX IDT

获取价格

 		Multiplexer, FCT Series, 1-Func, 8 Line Input, 1 Line Output, Complementary Output, CMOS,
5962-9220601MFA WEDC

获取价格

 		Multiplexer, FCT Series, 1-Func, 8 Line Input, 1 Line Output, Complementary Output, CMOS

与5962-9220504MLA相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证