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5962-9201601MEA

更新时间： 2024-02-13 22:12:23
品牌 Logo 应用领域
亚德诺 - ADI 信息通信管理转换器
页数 文件大小 规格书
8页 308K
描述
16-Bit Current-Steering DAC with Voltage Reference

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5962-9201601MEA 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：DIP
包装说明：CERAMIC, DIP-16针数：16
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.2
转换器类型：D/A CONVERTER输入位码：2'S COMPLEMENT BINARY
输入格式：SERIALJESD-30 代码：R-CDIP-T16
JESD-609代码：e0标称负供电电压：-5 V
位数：16功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：+-5/+-12 V
认证状态：Qualified筛选级别：MIL-STD-883
子类别：Other Converters最大压摆率：15 mA
标称供电电压：5 V表面贴装：NO
技术：BICMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

5962-9201601MEA 数据手册

 浏览型号5962-9201601MEA的Datasheet PDF文件第1页浏览型号5962-9201601MEA的Datasheet PDF文件第2页浏览型号5962-9201601MEA的Datasheet PDF文件第3页浏览型号5962-9201601MEA的Datasheet PDF文件第5页浏览型号5962-9201601MEA的Datasheet PDF文件第6页浏览型号5962-9201601MEA的Datasheet PDF文件第7页 
AD766–Definition of Specifications  
TOTAL HARMONIC DISTORTION  
FUNCTIONAL DESCRIPTION  
Total Harmonic Distortion (THD) is defined as the ratio of the  
square root of the sum of the squares of the values of the har-  
monics to the value of the fundamental input frequency. It is ex-  
pressed in percent (%) or decibels (dB).  
Serial input data is clocked into the AD766’s shift register by  
the falling edge of CLK. Data is presumed to be in twos  
complement format with MSB (i.e., the sign bit) clocked in first.  
The shift register converts the most recently clocked-in 16 bits  
to a parallel word. The falling edge of the latch enable (LE) sig-  
nal causes the most recent parallel word to be transferred to the  
internal DAC input latch. See Figure 2 for detailed serial port  
timing requirements.  
THD is a measure of the magnitude and distribution of integral  
linearity error and differential linearity error. The distribution of  
these errors may be different, depending on the amplitude of the  
output signal. Therefore, to be most useful, THD should be  
specified for both large and small signal amplitudes.  
The contents of the DAC input latch cause the 16-bit DAC to  
generate a corresponding current. This ±1 mA current is avail-  
able directly on the IOUT pin.  
SETTLING TIME  
Settling Time is the time required for the output to reach and  
remain within a specified error band about its final value, mea-  
sured from the digital input transition. It is the primary measure  
of dynamic performance.  
To use the internal op amp, connect IOUT (Pin 13) directly to  
the summing junction pin, SJ (Pin 11) and connect the feedback  
resistor pin, RF (Pin 10) to VOUT (Pin 9). Note that the internal  
op amp is in the inverting configuration. Using the internal  
3 kΩ feedback resistor, this op amp will produce ±3 V outputs.  
BIPOLAR ZERO ERROR  
One advantage of external pins at each end of the feedback  
resistor is that it allows the user to implement a single pole  
active low-pass filter simply by adding a capacitor across these  
pins (Pins 10 and 13). The circuit can best be understood  
redrawn as shown in Figure 1.  
Bipolar Zero Error or midscale error is the deviation of the ac-  
tual analog output from the ideal output (0 V) when the 2s  
complement input code representing half scale (all 0s) is loaded  
in the input register.  
DIFFERENTIAL LINEARITY ERROR  
Differential Linearity Error is the measure of the variation in  
analog value, normalized to full scale, associated with a 1 LSB  
change in the digital input. Monotonic behavior requires that  
the differential linearity error not exceed 1 LSB in the negative  
direction.  
MONOTONICITY  
A D/A converter is monotonic if the output either increases or  
remains constant as the digital input increases.  
Figure 1. Low-Pass Filter Using External Capacitor  
The frequency response from this filter will be  
SIGNAL-TO-NOISE RATIO  
SNR is defined as the ratio of the fundamental to the square  
root of the sum of the squares for the values of all the nonfun-  
damental, nonharmonic signals for a specified bandwidth. SNR  
is tested at full-scale input. The AD766 specifies SNR for  
20 kHz and 250 kHz bandwidths.  
V
OUT (s)  
IOUT  
−RF  
s +1  
=
RF  
•
C
•
where RF is 3 kΩ (±20%).  
Figure 2. AD766 Serial Input Timing  
REV. A  
–4–  
12345678

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