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5962-9162701MCA PDF预览

5962-9162701MCA

更新时间: 2024-01-03 21:16:15
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德州仪器 - TI 栅极
页数 文件大小 规格书
5页 83K
描述
军用 4 通道、2 输入、4.5V 至 5.5V 双极与非门 | J | 14 | -55 to 125

5962-9162701MCA 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:0.300 INCH, CERAMIC, DIP-14针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.58Is Samacsys:N
其他特性:IOH = 40MA @ VOH = 2V; IOL = 40MA @ VOL = 0.5V系列:AS
JESD-30 代码:R-GDIP-T14长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.04 A功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):19 mA
Prop。Delay @ Nom-Sup:5 ns传播延迟(tpd):5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

5962-9162701MCA 数据手册

 浏览型号5962-9162701MCA的Datasheet PDF文件第1页浏览型号5962-9162701MCA的Datasheet PDF文件第2页浏览型号5962-9162701MCA的Datasheet PDF文件第3页浏览型号5962-9162701MCA的Datasheet PDF文件第5页 
SN54AS1000A, SN74AS1000A  
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS/DRIVERS  
SDAS056B – APRIL 1984 – REVISED JANUARY 1995  
PARAMETER MEASUREMENT INFORMATION  
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES  
7 V  
R
= R1 = R2  
V
CC  
L
S1  
R1  
R
L
Test  
Point  
From Output  
Under Test  
From Output  
Under Test  
Test  
Point  
Test  
Point  
From Output  
Under Test  
C
C
L
R
L
R2  
L
C
L
(see Note A)  
(see Note A)  
(see Note A)  
LOAD CIRCUIT FOR  
BI-STATE  
TOTEM-POLE OUTPUTS  
LOAD CIRCUIT  
FOR OPEN-COLLECTOR OUTPUTS  
LOAD CIRCUIT  
FOR 3-STATE OUTPUTS  
3.5 V  
3.5 V  
Timing  
Input  
High-Level  
1.3 V  
1.3 V  
1.3 V  
Pulse  
0.3 V  
0.3 V  
t
h
t
w
t
su  
3.5 V  
3.5 V  
0.3 V  
Data  
Input  
Low-Level  
1.3 V  
1.3 V  
1.3 V  
1.3 V  
Pulse  
0.3 V  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
VOLTAGE WAVEFORMS  
PULSE DURATIONS  
3.5 V  
0.3 V  
Output  
Control  
(low-level  
enabling)  
1.3 V  
1.3 V  
3.5 V  
t
PZL  
Input  
1.3 V  
1.3 V  
t
PLZ  
0.3 V  
PHL  
3.5 V  
t
Waveform 1  
S1 Closed  
(see Note B)  
t
PLH  
1.3 V  
V
OH  
In-Phase  
Output  
1.3 V  
1.3 V  
1.3 V  
V
OL  
0.3 V  
V
OL  
t
PHZ  
t
PLH  
t
PZH  
t
PHL  
V
OH  
V
Waveform 2  
S1 Open  
(see Note B)  
OH  
OL  
Out-of-Phase  
Output  
(see Note C)  
1.3 V  
1.3 V  
0.3 V  
V
0 V  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.  
D. All input pulses have the following characteristics: PRR 1 MHz, t = t = 2 ns, duty cycle = 50%.  
r
f
E. The outputs are measured one at a time with one transition per measurement.  
Figure 1. Load Circuits and Voltage Waveforms  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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