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5962-9054901MQA PDF预览

5962-9054901MQA

更新时间: 2024-02-09 23:21:24
品牌 Logo 应用领域
英特矽尔 - INTERSIL 解码器电信集成电路编码器
页数 文件大小 规格书
16页 267K
描述
CMOS Manchester Encoder-Decoder

5962-9054901MQA 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.78JESD-30 代码:R-GDIP-T40
功能数量:1端子数量:40
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
筛选级别:MIL-STD-883标称供电电压:5 V
表面贴装:NO技术:CMOS
电信集成电路类型:MANCHESTER ENCODER/DECODER温度等级:MILITARY
端子形式:THROUGH-HOLE端子位置:DUAL
Base Number Matches:1

5962-9054901MQA 数据手册

 浏览型号5962-9054901MQA的Datasheet PDF文件第3页浏览型号5962-9054901MQA的Datasheet PDF文件第4页浏览型号5962-9054901MQA的Datasheet PDF文件第5页浏览型号5962-9054901MQA的Datasheet PDF文件第7页浏览型号5962-9054901MQA的Datasheet PDF文件第8页浏览型号5962-9054901MQA的Datasheet PDF文件第9页 
HD-15531  
ting the decoded data through SERIAL DATA OUT. The on VALID WORD output 4 indicates a successful reception  
decoded data available at SERIAL DATA OUT is in NRZ of a word without any Manchester or parity errors. At this  
format. The DECODER SHIFT CLOCK is provided so that time the Decoder is looking for a new sync character to start  
the decoded bits can get shifted into an external register on another output sequence. VALID WORD will go low approx-  
every low-to-high transition of this clock  
DECODER SHIFT CLOCK may adjust its phase up until the goes high, if not reset low sooner by a valid sync and two  
time that TAKE DATA goes high. valid Manchester bits as shown 1 .  
2 - 3 . Note that imately K + 4 DECODER SHIFT CLOCK periods after it  
After all K decoded bits have been transmitted 3 the data is At any time in the above sequence a high input on  
checked for parity. A high input on DECODER PARITY DECODER RESET during low-to-high transition of  
a
SELECT will set the Decoder to check for even parity or a DECODER SHIFT CLOCK will abort transmission and ini-  
low input will set the Decoder to check for odd parity. A high tialize the Decoder to start looking for a new sync character.  
TIMING  
0
1
2
3
4
5
6
7
8
N-3  
N-2  
N-1  
N
SYNCHRONOUS  
CLOCK  
DECODER  
SHIFT  
CLOCK  
BIPOLAR  
ONE IN  
1ST HALF  
SYNC  
BITK-1  
BITK-5  
BIT 3 BIT 2 BIT 1 PARITY  
BIT 3 BIT 2 BIT 1 PARITY  
2ND HALF  
SYNC  
BITK-2  
BITK-4  
MSB  
BITK-3  
BIPOLAR  
ZERO IN  
MSB BITK-1 BITK-2 BIT K-3 BITK-4 BITK-5  
TAKE DATA  
COMMAND  
SYNC  
DATA SYNC  
SERIAL  
DATA OUT  
UNDEFINED  
(MAY BE HIGH FROM PREVIOUS RECEPTION)  
MSB BITK-1 BITK-2 BITK-3  
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1  
VALID WORD  
1
2
3
4
FIGURE 2. DECODER  
6

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