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5962-9054901MQA PDF预览

5962-9054901MQA

更新时间： 2024-02-04 12:55:34
品牌 Logo 应用领域
英特矽尔 - INTERSIL 解码器电信集成电路编码器
页数 文件大小 规格书
16页 267K
描述
CMOS Manchester Encoder-Decoder

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5962-9054901MQA 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.78JESD-30 代码：R-GDIP-T40
功能数量：1端子数量：40
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装形状：RECTANGULAR
封装形式：IN-LINE认证状态：Not Qualified
筛选级别：MIL-STD-883标称供电电压：5 V
表面贴装：NO技术：CMOS
电信集成电路类型：MANCHESTER ENCODER/DECODER温度等级：MILITARY
端子形式：THROUGH-HOLE端子位置：DUAL
Base Number Matches：1

5962-9054901MQA 数据手册

 浏览型号5962-9054901MQA的Datasheet PDF文件第1页浏览型号5962-9054901MQA的Datasheet PDF文件第2页浏览型号5962-9054901MQA的Datasheet PDF文件第4页浏览型号5962-9054901MQA的Datasheet PDF文件第5页浏览型号5962-9054901MQA的Datasheet PDF文件第6页浏览型号5962-9054901MQA的Datasheet PDF文件第7页 
HD-15531  
DECODER  
7
8
SYNCHRONOUS  
DATA SELECT  
SYNCHRONOUS  
DATA  
13  
UNIPOLAR  
DATA IN  
4
TAKE DATA  
DATA  
SELECT  
GATE  
12  
11  
17  
TRANSITION  
FINDER  
CHARACTER  
IDENTIFIER  
BIPOLAR  
ONE IN  
COMMAND SYNC  
BIPOLAR  
ONE IN  
DATA SYNC  
5
SERIAL  
DATA OUT  
9
2
DECODER  
CLK  
VALID WORD  
CLOCK  
SELECT  
DATA  
BIT  
RATE  
CLK  
PARITY  
SYNCHRONIZER  
16  
CHECK  
PARITY  
SELECT  
15  
DECODER  
CLK SELECT  
8
SYNCHRONOUS  
CLK  
14  
DECODER  
SHIFT CLK  
10  
22  
SYNCHRONOUS  
CLK SELECT  
MASTER  
RESET  
19  
3
BIT  
COUNTER  
DECODER  
RESET  
TAKE DATA’  
20 40 23 36 39  
C
C
C
C
C
4
0
1
2
3
Pin Description  
PIN  
NUMBER TYPE  
NAME  
SECTION  
DESCRIPTION  
1
V
Both  
Positive supply pin. A 0.1µF decoupling capacitor from V  
(pin 1) to GROUND  
CC  
CC  
(pin 21) is recommended.  
2
3
O
O
VALID WORD  
TAKE DATA’  
Decoder Output high indicates receipt of a valid word, (valid parity and no Manchester  
errors).  
Decoder A continuous, free running signal provided for host timing or data handling. When  
data is present on the bus, this signal will be synchronized to the incoming data  
and will be identical to TAKE DATA.  
4
O
TAKE DATA  
Decoder Output is high during receipt of data after identification of a valid sync pulse and  
two valid Manchester bits.  
5
6
O
I
SERIAL DATA OUT  
Decoder Delivers received data in correct NRZ format.  
SYNCHRONOUS  
DATA  
Decoder Input presents Manchester data directly to character identification logic.  
SYNCHRONOUS DATA SELECT must be held high to use this input. If not  
used, this pin must be held high.  
7
I
I
I
I
I
I
I
SYNCHRONOUS  
DATA SELECT  
Decoder In high state allows the synchronous data to enter the character identification  
logic. Tie this input low for asynchronous data.  
8
SYNCHRONOUS  
CLOCK  
Decoder Input provides externally synchronized clock to the decoder, for use when re-  
ceiving synchronous data. This input must be tied high when not in use.  
9
DECODER CLOCK  
Decoder Input drives the transition finder, and the synchronizer which in turn supplies the  
clock to the balance of the decoder. Input a frequency equal to 12X the data rate.  
10  
11  
12  
13  
SYNCHRONOUS  
CLOCK SELCT  
Decoder In high state directs the SYNCHRONOUS CLOCK to control the decoder char-  
acter identification logic. A low state selects the DECODER CLOCK.  
BIPOLAR ZERO IN  
BIPOLAR ONE IN  
UNIPOLAR DATA IN  
Decoder A high input should be applied when the bus is in its negative state. This pin must  
be held high when the unipolar input is used.  
Decoder A high input should be applied when the bus is in its positive state. This pin must  
he held low when the unipolar input is used.  
Decoder With pin 11 high and pin 12 low, this pin enters unipolar data into the transition  
finder circuit. If not used this input must be held low.  
3
1234567...16

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