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5962-8973001LA PDF预览

5962-8973001LA

更新时间: 2024-02-20 07:51:34
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
7页 83K
描述
CDIP-24, Tube

5962-8973001LA 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.26其他特性:MASTER CONTROL FOR LATCH AND OUTPUT ENABLES IN EACH DIRECTION
系列:FCTJESD-30 代码:R-GDIP-T24
JESD-609代码:e0长度:32.004 mm
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):14 ns
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

5962-8973001LA 数据手册

 浏览型号5962-8973001LA的Datasheet PDF文件第1页浏览型号5962-8973001LA的Datasheet PDF文件第2页浏览型号5962-8973001LA的Datasheet PDF文件第3页浏览型号5962-8973001LA的Datasheet PDF文件第4页浏览型号5962-8973001LA的Datasheet PDF文件第5页浏览型号5962-8973001LA的Datasheet PDF文件第7页 
IDT54/74FCT543/A/C  
FASTCMOSOCTALLATCHEDTRANSCEIVER  
MILITARYANDCOMMERCIAL TEMPERATURERANGES  
TESTCIRCUITSANDWAVEFORMS  
VCC  
7.0V  
SWITCHPOSITION  
500Ω  
Test  
Switch  
Closed  
Open  
VOUT  
VIN  
Open Drain  
Disable Low  
Enable Low  
Pulse  
Generator  
D.U.T  
.
50pF  
All Other Tests  
500Ω  
RT  
L
C
DEFINITIONS:  
CL = Load capacitance: includes jig and probe capacitance.  
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.  
Octal link  
Test Circuits for All Outputs  
3V  
DATA  
1.5V  
0V  
INPUT  
LOW-HIGH-LOW  
PULSE  
tH  
tSU  
1.5V  
1.5V  
3V  
1.5V  
0V  
TIMING  
INPUT  
tW  
ASYNCHRONOUS CONTROL  
tREM  
PRESET  
3V  
1.5V  
0V  
CLEAR  
HIGH-LOW-HIGH  
PULSE  
ETC.  
SYNCHRONOUS CONTROL  
PRESET  
3V  
Octal link  
1.5V  
0V  
CLEAR  
tSU  
tH  
CLOCK ENABLE  
ETC.  
Pulse Width  
Octal link  
Set-Up, Hold, and Release Times  
ENABLE  
DISABLE  
3V  
1.5V  
0V  
3V  
SAME PHASE  
CONTROL  
INPUT  
1.5V  
0V  
INPUT TRANSITION  
tPLH  
tPLH  
tPHL  
tPHL  
tPZL  
tPLZ  
VOH  
1.5V  
VOL  
OUTPUT  
3.5V  
1.5V  
3.5V  
VOL  
VOH  
OUTPUT  
NORMALLY  
LOW  
SWITCH  
CLOSED  
0.3V  
0.3V  
3V  
1.5V  
0V  
tPZH  
tPHZ  
OPPOSITE PHASE  
INPUT TRANSITION  
OUTPUT  
NORMALLY  
HIGH  
SWITCH  
OPEN  
1.5V  
0V  
Octal link  
0V  
Octal link  
Propagation Delay  
Enable and Disable Times  
NOTES:  
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.  
2. Pulse Generator for All Pulses: Rate 1.0MHz; ZO 50; tF 2.5ns; tR 2.5ns.  
6

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