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5962-8876404XX PDF预览

5962-8876404XX

更新时间: 2024-01-17 01:41:38
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
16页 286K
描述
High Speed , 8-Channel, 8-Bit CMOS ADC

5962-8876404XX 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:28
Reach Compliance Code:unknown风险等级:5.7
Is Samacsys:N最大模拟输入电压:5 V
最小模拟输入电压:最长转换时间:2 µs
转换器类型:ADC, FLASH METHODJESD-30 代码:R-GDIP-T28
JESD-609代码:e0湿度敏感等级:NOT APPLICABLE
模拟输入通道数量:8位数:8
功能数量:1端子数量:28
最高工作温度:125 °C最低工作温度:-55 °C
输出位码:BINARY, COMPLEMENTARY OFFSET BINARY输出格式:PARALLEL, 8 BITS
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT APPLICABLE采样速率:0.05 MHz
采样并保持/跟踪并保持:TRACK座面最大高度:5.59 mm
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT APPLICABLE宽度:15.24 mm
Base Number Matches:1

5962-8876404XX 数据手册

 浏览型号5962-8876404XX的Datasheet PDF文件第1页浏览型号5962-8876404XX的Datasheet PDF文件第2页浏览型号5962-8876404XX的Datasheet PDF文件第4页浏览型号5962-8876404XX的Datasheet PDF文件第5页浏览型号5962-8876404XX的Datasheet PDF文件第6页浏览型号5962-8876404XX的Datasheet PDF文件第7页 
AD7824/AD7828  
TIMING CHARACTERISTICS1  
(VDD = 5 V; VREF(+) = 5 V; VREF(–) = GND = 0 V, unless otherwise noted.)  
Limit at 25؇C  
Limit at TMIN, TMAX  
Limit at TMIN, TMAX  
Parameter  
(All Grades)  
(K, L, B, C Grades)  
(T, U Grades)  
Unit  
Conditions/Comments  
tCSS  
tCSH  
tAS  
tAH  
tRDY  
0
0
0
30  
40  
0
0
0
35  
60  
0
0
0
40  
60  
ns min  
ns min  
ns min  
ns min  
ns max  
CS to RD Setup Time  
CS to RD Hold Time  
Multiplexer Address Setup Time  
Multiplexer Address Hold Time  
CS to RDY Delay. Pull-Up  
Resistor 5 k.  
Conversion Time, Mode 0  
Data Access Time after RD  
Data Access Time after INT, Mode 0  
RD to INT Delay  
2
tCRD  
tACC1  
tACC2  
tlNTH  
2.0  
85  
50  
2.4  
110  
60  
2.8  
120  
70  
µs max  
ns max  
ns max  
ns typ  
3
3
2
40  
65  
70  
75  
60  
500  
60  
600  
100  
70  
500  
80  
100  
70  
600  
80  
ns max  
ns max  
ns min  
ns min  
ns max  
4
tDH  
tP  
tRD  
Data Hold Time  
Delay Time between Conversions  
Read Pulsewidth, Mode 1  
500  
400  
NOTES  
1Sample tested at 25°C to ensure compliance. All input control signals are specified with tRISE = tFALL = 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.  
2CL = 50 pF.  
3Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.  
4Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.  
Specifications subject to change without notice.  
Test Circuits  
DBN  
DBN  
3k  
10pF  
3k⍀  
100pF  
DGND  
DGND  
a. VOH to High-Z  
a. High-Z to VOH  
5V  
5V  
3k  
3k⍀  
DBN  
DBN  
10pF  
DGND  
100pF  
DGND  
b. VOL to High-Z  
b. High-Z to VOL  
Figure 2. Load Circuits for Data Hold Time Test  
Figure 1. Load Circuits for Data Access Time Test  
REV. F  
–3–  

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