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5962-88735033X PDF预览

5962-88735033X

更新时间： 2024-02-24 16:22:22
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 可编程只读存储器OTP只读存储器输出元件内存集成电路
页数 文件大小 规格书
12页 925K
描述
2KX8 OTPROM, 15ns, CQCC28

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5962-88735033X 技术参数

生命周期：Transferred包装说明：QCCN,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.27
Is Samacsys：N最长访问时间：15 ns
其他特性：PROGRAMMABLE SYNCHRONOUS OR ASYNCHRONOUS OUTPUT ENABLE; PROGRAMMABLE ASYNCHRONOUS REGISTERSJESD-30 代码：S-CQCC-N28
内存密度：16384 bit内存集成电路类型：OTP ROM
内存宽度：8功能数量：1
端子数量：28字数：2048 words
字数代码：2000工作模式：SYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：2KX8封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL
认证状态：Not Qualified最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：NO LEAD
端子位置：QUADBase Number Matches：1

5962-88735033X 数据手册

 浏览型号5962-88735033X的Datasheet PDF文件第1页浏览型号5962-88735033X的Datasheet PDF文件第2页浏览型号5962-88735033X的Datasheet PDF文件第3页浏览型号5962-88735033X的Datasheet PDF文件第5页浏览型号5962-88735033X的Datasheet PDF文件第6页浏览型号5962-88735033X的Datasheet PDF文件第7页 
CY7C245A  
AC Test Loads and Waveforms[3, 4]  
R1 250Ω  
R1 250Ω  
5V  
5V  
ALL INPUT PULSES  
3.0V  
GND  
OUTPUT  
OUTPUT  
90%  
10%  
90%  
10%  
R2  
167Ω  
R2  
167Ω  
50 pF  
5 pF  
≤
5 ns  
5 ns  
≤
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(a) Normal Load  
(b) HighZ Load  
Equivalent to: THÉVENIN EQUIVALENT  
100Ω  
OUTPUT  
2.0V  
Switching Characteristics Over Operating Range[3, 4]  
7C245A-15 7C245A-18 7C245A-35  
7C245A-25  
7C245A-35  
Parameter  
tSA  
Description  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit  
Address Set-Up to Clock HIGH  
Address Hold from Clock HIGH  
Clock HIGH to Valid Output  
Clock Pulse Width  
15  
0
18  
0
25  
0
35  
0
45  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tHA  
tCO  
10  
15  
12  
20  
12  
20  
15  
20  
25  
35  
tPWC  
tSES  
tHES  
tDI  
10  
10  
5
12  
10  
5
15  
12  
5
20  
15  
5
20  
15  
5
ES Set-Up to Clock HIGH  
ES Hold from Clock HIGH  
Delay from INIT to Valid Output  
INIT Recovery to Clock HIGH  
INIT Pulse Width  
tRI  
10  
10  
12  
12  
15  
15  
20  
20  
20  
25  
tPWI  
tCOS  
tHZC  
Valid Output from Clock HIGH[7]  
15  
15  
15  
15  
15  
15  
20  
20  
30  
30  
Inactive Output from Clock  
HIGH[7]  
tDOE  
Valid Output from E LOW[8]  
Inactive Output from E HIGH[8]  
12  
15  
15  
15  
15  
15  
20  
20  
30  
30  
ns  
ns  
tHZE  
Notes:  
7. Applies only when the synchronous (ES) function is used.  
8. Applies only when the asynchronous (E) function is used.  
to the enable input. The stored data is accessed and loaded into the  
master flip-flops of the data register during the address set-up time.  
At the next LOW-to-HIGH transition of the clock (CP), data is trans-  
ferred to the slave flip-flops, which drive the output buffers, and the  
accessed data will appear at the outputs (O0–O7).  
Operating Modes  
The CY7C245A is a CMOS electrically programmable read  
only memory organized as 2048 words x 8 bits and is a  
pin-for-pin replacement for bipolar TTL fusible link PROMs.  
The CY7C245A incorporates a D-type, master-slave register  
on chip, reducing the cost and size of pipelined micropro-  
grammed systems and applications where accessed PROM  
data is stored temporarily in a register. Additional flexibility is  
If the asynchronous enable (E) is being used, the outputs may be  
disabledat anytime by switching the enabletoa logic HIGH, and may  
be returned to the active state by switching the enable to a logic LOW.  
If the synchronous enable (ES) is being used, the outputs will go  
to theOFF or high-impedance state uponthe next positive clock edge  
after the synchronous enable input is switched to a HIGH level. If the  
synchronous enable pin is switched to a logic LOW, the subsequent  
positive clock edge will return the output to the active state. Following  
a positive clock edge, the address and synchronous enable inputs  
are free to change since no change in the output will occur until the  
next LOW-to-HIGH transition of the clock. This unique feature allows  
theCY7C245A decoders and sense amplifiers to access the next  
location while previously addressed data remains stable on  
the outputs.  
provided with  
a
programmable synchronous (ES) or  
asynchronous (E) output enable and asynchronous initialization  
(INIT).  
Upon power-up the state of the outputs will depend on the  
programmed state of the enable function (ES or E). If the  
synchronous enable (ES) has been programmed, the register will be  
in the set condition causing the outputs (O0–O7) to be in the OFF or  
high-impedance state. If the asynchronous enable (E) is being used,  
the outputs will come up in the OFF or high-impedance state only if  
the enable (E) input is at a HIGH logic level. Data is read by applying  
the memory location to the address inputs (A0–A10) and a logic LOW  
Document #: 38-04007 Rev. *B  
Page 3 of 11  
1234567...12

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