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5962-8778902EA PDF预览

5962-8778902EA

更新时间: 2024-01-03 05:47:58
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
8页 332K
描述
Voltage-output 8-bit digital-to-analog converter, including output amplifier, full microprocessor interface and precision

5962-8778902EA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.62
Is Samacsys:N最大模拟输出电压:10 V
最小模拟输出电压:转换器类型:D/A CONVERTER
输入位码:BINARY输入格式:PARALLEL, 8 BITS
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.05 mm位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Qualified
筛选级别:MIL-STD-883座面最大高度:5.08 mm
标称供电电压:5 V表面贴装:NO
技术:BIPOLAR温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

5962-8778902EA 数据手册

 浏览型号5962-8778902EA的Datasheet PDF文件第2页浏览型号5962-8778902EA的Datasheet PDF文件第3页浏览型号5962-8778902EA的Datasheet PDF文件第4页浏览型号5962-8778902EA的Datasheet PDF文件第6页浏览型号5962-8778902EA的Datasheet PDF文件第7页浏览型号5962-8778902EA的Datasheet PDF文件第8页 
Applications–AD558  
The only consideration in selecting a supply voltage is that, in  
order to be able to use the 0 V to 10 V output range, the power  
supply voltage must be between +11.4 V and +16.5 V. If, how-  
ever, the 0 V to 2.56 V range is to be used, power consumption  
will be minimized by utilizing the lowest available supply voltage  
(above +4.5 V).  
OUTPUT  
AMP  
V
16  
15  
14  
13  
OUT  
604Ω  
500Ω  
40kΩ  
2kΩ  
14kΩ  
TIMING AND CONTROL  
GND  
The AD558 has data input latches that simplify interface to 8-  
and 16-bit data buses. These latches are controlled by Chip  
Enable (CE) and Chip Select (CS) inputs. CE and CS are inter-  
nally “NORed” so that the latches transmit input data to the  
DAC section when both CE and CS are at Logic “0”. If the ap-  
plication does not involve a data bus, a “00” condition allows  
for direct operation of the DAC. When either CE or CS go to  
Logic “1”, the input data is latched into the registers and held  
until both CE and CS return to “0”. (Unused CE or CS inputs  
should be tied to ground.) The truth table is given in Table I.  
The logic function is also shown in Figure 6.  
Figure 4. 10.24 V Full-Scale Connection  
NOTE: Decreasing the scale by putting a resistor in series with GND  
will not work properly due to the code-dependent currents in GND.  
Adjusting offset by injecting dc at GND is not recommended for the  
same reason.  
GROUNDING AND BYPASSING*  
All precision converter products require careful application of  
good grounding practices to maintain full rated performance.  
Because the AD558 is intended for application in microcom-  
puter systems where digital noise is prevalent, special care must  
be taken to assure that its inherent precision is realized.  
Table I. AD558 Control Logic Truth Table  
Latch  
The AD558 has two ground (common) pins; this minimizes  
ground drops and noise in the analog signal path. Figure 5  
shows how the ground connections should be made.  
Input Data  
CE  
CS  
DAC Data  
Condition  
0
1
0
1
0
1
X
X
0
0
g
g
0
0
1
X
0
0
0
0
g
g
X
1
0
1
0
1
0
1
“Transparent”  
“Transparent”  
Latching  
Latching  
Latching  
OUTPUT  
AMP  
V
OUT  
16  
Latching  
V
V
SENSE  
OUT  
Previous Data Latched  
Previous Data Latched  
15  
14  
13  
12  
11  
(SEE NEXT  
PAGE)  
SELECT  
OUT  
R
L
NOTES  
GND  
X = Does not matter.  
g = Logic Threshold at Positive-Going Transition.  
TO SYSTEM GND  
TO SYSTEM GND  
(SEE TEXT)  
GND  
0.1µF  
TO SYSTEM V  
CC  
+V  
CC  
Figure 5. Recommended Grounding and Bypassing  
It is often advisable to maintain separate analog and digital  
grounds throughout a complete system, tying them common in  
one place only. If the common tie-point is remote and acciden-  
tal disconnection of that one common tie-point occurs due to  
card removal with power on, a large differential voltage between  
the two commons could develop. To protect devices that inter-  
face to both digital and analog parts of the system, such as the  
AD558, it is recommended that common ground tie-points  
should be provided at each such device. If only one system  
ground can be connected directly to the AD558, it is recom-  
mended that analog common be selected.  
Figure 6. AD558 Control Logic Function  
In a level-triggered latch such as that in the AD558 there is an  
interaction between data setup and hold times and the width of  
the enable pulse. In an effort to reduce the time required to test  
all possible combinations in production, the AD558 is tested  
with tDS = tW = 200 ns at 25°C and 270 ns at TMIN and TMAX  
with tDH = 10 ns at all temperatures. Failure to comply with  
these specifications may result in data not being latched properly.  
,
POWER SUPPLY CONSIDERATIONS  
The AD558 is designed to operate from a single positive power  
supply voltage. Specified performance is achieved for any supply  
voltage between +4.5 V and +16.5 V. This makes the AD558  
ideal for battery-operated, portable, automotive or digital main-  
frame applications.  
Figure 7 shows the timing for the data and control signals; CE  
and CS are identical in timing as well as in function.  
*For additional insight, “An IC Amplifier Users’ Guide to Decoupling,  
Grounding and Making Things Go Right For A change,” is available  
at no charge from any Analog Devices Sales Office.  
REV. A  
–5–  

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