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5962-8774201VEA

更新时间： 2024-02-23 14:02:55

品牌	Logo	应用领域
德州仪器 - TI		稳压器电源电路电源管理电路
页数	文件大小	规格书
9页	676K
描述
High Efficiency Linear Regulator

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5962-8774201VEA 技术参数

生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	16
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	5.13	Is Samacsys：	N
其他特性：	UNDER AND OVER-VOLTAGE FAULT ALERT WITH PROGRAMMABLE DELAY	可调阈值：	YES
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT	JESD-30 代码：	R-GDIP-T16
长度：	19.56 mm	信道数量：	1
功能数量：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-55 °C
最大输出电压：	1.515 V	最小输出电压：	1.485 V
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Qualified
筛选级别：	MIL-PRF-38535 Class V	座面最大高度：	5.08 mm
最大供电电压 (Vsup)：	35 V	最小供电电压 (Vsup)：	5 V
标称供电电压 (Vsup)：	15 V	表面贴装：	NO
技术：	BIPOLAR	温度等级：	MILITARY
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	阈值电压标称：	0.15
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

5962-8774201VEA 数据手册

UC1834

UC2834

UC3834

APPLICATION INFORMATION

Foldback Current Limiting

Both the current sense and error amplifiers on the UC1834 The crowbar output on the UC1834 is activated following a

are transconductance type amplifiers. As a result, their volt- sustained over-voltage condition. The crowbar output remains

age gain is a direct function of the load impedance at their high as long as the fault condition persists, or, as long as the

shared output pin, Pin 14. Their small signal voltage gain as over-voltage latch is set. The latch is set with an over-voltage

a function of load and frequency is nominally given by;

fault if the voltage at Pin 15 is above the latch reset threshold,

typically 0.4V. When the latch is set, its Q− output will pull Pin

15 low through a series diode. As long as a nominal pull-up

load exists, the series diode prevents Q− from pulling Pin 15

below the reset threshold. However, Pin 15 is pulled low

enough to disable the driver outputs if Pins 15 and 14 are

tied together. With Pin 15 and 14 common, the regulator

will latch off in response to an over-voltage fault. If the

fault condition is cleared and Pins 14 and 15 are momen-

tarily pulled below the latch reset threshold, the driver out-

puts are re-enabled.

ZL (f)

70Ω

AV E ⁄ A =

and AV C. S. ⁄ A =

700Ω

for: f ≤ 500kHz and |ZL(f)| ≤ 1 MΩ

Where:

AV=Small Signal Voltage Gain to pin 14.

ZL(f) = Load Impedance at Pin 14.

The UC1834 fault delay circuitry prevents the fault outputs

from responding to transient fault conditions. The delay reset

latch insures that the full, user defined, delay passes before an

over-voltage fault response occurs. This prevents unnecessary

crowbar, or latched-off conditions, from occurring following

sharp under-voltage to over-voltage transients.

Setting the Threshold Adjust Voltage (VADJ)

1 2 3 456 7 8 9

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