AFE7222
AFE7225
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SLOS711B –NOVEMBER 2011–REVISED MARCH 2012
Table 2-2. Pin Configuration: LVDS Input/Output Mode (continued)
PIN
DESCRIPTION
NO.
9
NAME
CLKINP
main clock input, positive side if differential mode, RX side if single-ended 2 clock mode
1.8V supply for Clocking circuit
10
11
12
13
14
15
16
17
DVDD18_CLK
AVDD3_DAC
IOUTP_A_DAC
IOUTN_A_DAC
AVDD3_DAC
IOUTP_B_DAC
IOUTN_B_DAC
AVDD3_DAC
3V supply for TX DACs
TX DAC channel A current output, positive (current sink DACs)
TX DAC channel A current output, negative (current sink DACs)
3V supply for TX DACs
TX DAC channel B current output, positive (current sink DACs)
TX DAC channel B current output, negative (current sink DACs)
3V supply for TX DACs
sets the TX DAC output current (resistor from pin to ground). Use 960 Ohm to set a full scale current of
20 mA.
18
BIASJ
19
20
DVDD18_DAC
AUXDAC_A
AUXDAC_B
AVDD3_AUX
AUXADC_A
AUXADC_B
AVDD18_ADC
1.8V DAC digital supply
auxiliary DAC channel A output, current sourcing up to 7.5mA (SPI programmable)
21
auxiliary DAC channel B output, current sourcing up to 7.5mA (SPI programmable)
22
3V supply for auxiliary ADC/DACs
23
auxiliary ADC channel A input
24
auxiliary ADC channel B input
25
1.8V supply for RX ADCs
26, 27
26
LVDS Wire 1 data input for Channel A TX data – inactive in 1-wire mode, LSB byte in 2-wire mode
DAC_DATA_11
DAC_DATA_10
Positive
27
Negative
28, 29
28
LVDS Wire 0 data input for Channel A TX data – active in 1-wire mode, MSB byte in 2-wire mode
DAC_DATA_9
DAC_DATA_8
Positive
29
Negative
30, 31
30
LVDS frame clock input
DAC_FCLKINP
DAC_FCLKINN
DVDD18
Positive
31
Negative
32
1.8V supply for digital interface
33, 34
33
LVDS bit clock input
DAC_DCLKINP
DAC_DCLKINN
Positive
34
Negative
35, 36
35
LVDS Wire 0 data input for Channel B TX data – active in 1-wire mode, LSB byte in 2-wire mode
DACB_DATA_0P
DACB_DATA_0N
Positive
36
Negative
37, 38
37
LVDS Wire 1 data input for Channel B TX data – inactive in 1-wire mode, MSB byte in 2-wire mode
DACB_DATA_1P
DACB_DATA_1N
Positive
38
Negative
39, 40
39
LVDS SYNC input – Used to reset internal clock dividers and reset TX data FIFO pointer
SYNCINP
SYNCINN
DVDD18
Positive
40
Negative
41
1.8V supply for digital interface
42, 43
42
LVDS Wire 1 data output for Channel B RX data – inactive in 1-wire mode, MSB byte in 2-wire mode
ADCB_DATA_1N
ADCB_DATA_1P
Positive
43
Negative
44, 45
44
LVDS Wire 0 data output for Channel B RX data – active in 1-wire mode, LSB byte in 2-wire mode
ADCB_DATA_0N
ADCB_DATA_0P
Positive
45
Negative
Copyright © 2011–2012, Texas Instruments Incorporated
DEVICE INFORMATION
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