3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available
onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit
group number 41 (see MIL-PRF-38535, appendix A).
3.11 Processing of EEPROMs. All testing requirements and quality assurance provisions herein shall be satisfied by the
manufacturer prior to delivery.
3.11.1 Conditions of the supplied devices. Devices will be supplied in an unprogrammed or clear state. No provision will be
made for supplying programmed devices.
3.11.2 Erasure of EEPROMs. When specified, devices shall be erased in accordance with procedures and characteristics
specified in 4.5.1.
3.11.3 Programming of EEPROMs. When specified, devices shall be programmed in accordance with procedures and
characteristics specified in 4.5.2.
3.11.4 Verification of state of EEPROMs. When specified, devices shall be verified as either written to the specified pattern
or cleared. As a minimum, verification shall consist of performing a read of the entire array to verify that all bits are in the proper
state. Any bit that does not verify to be in the proper state shall constitute a device failure and the device shall be removed from
the lot or sample.
3.11.5 Power supply sequence of EEPROMs. In order to reduce the probability of inadvertant writes, the following power
supply sequences shall be observed.
a. For device types 1-19, a logic high state shall be applied to WE and/or CE at the same time or before the application
of V . For device types 16-19, an additional precaution is available, a logic low state shall be applied to RES at the
CC
same time or before the application of V
.
CC
b. For device types 1-19, a logic high state shall be applied to WE and/or CE at the same time or before the removal of
V
. For device types 16-19, an additional precaution is available, a logic low state shall be applied to RES at the
CC
same time or before the removal of V
.
CC
3.12 Endurance. A reprogrammability test shall be completed as part of the vendor's reliability monitors. This
reprogrammability test shall be done for initial characterization and after any design or process changes which may affect the
reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of
program/erase endurance cycles listed in section 1.3 herein over the full military temperature range. The vendor's procedure
shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with
test data.
3.13 Data retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test shall
be done for initial characterization and after any design or process change which may affect data retention. The methods and
procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military
temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request
of the acquiring or preparing activity, along with test data.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-38267
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
G
SHEET
6
DSCC FORM 2234
APR 97
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