Datasheet > 5962-1022401KXA

5962-1022401KXA

更新时间： 2024-02-18 12:34:03

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
11页	99K
描述
Analog Circuit, Hybrid,

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技术参数
数据手册

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5962-1022401KXA 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	,	Reach Compliance Code：	unknown
风险等级：	5.8	Is Samacsys：	N
认证状态：	Not Qualified	子类别：	Other Analog ICs
Base Number Matches：	1

5962-1022401KXA 数据手册

TABLE I. Electrical performance characteristics - Continued.

Test

Symbol

Conditions

Group A

subgroups

Device

type

Limits

Min

Unit

-55C  T +85C

Max

V_IN= 28V DC ± 5%, C_L= 0

unless otherwise specified

Line Rejection 2/ 4/ 1/

REJ

ENB

100% load, DC to 50 kHz ,

Enable Input (Inhibit) 1/

Open circuit voltage

5.0

Drive current (sink) 1/

Voltage range 1/

-0.5

-300

Output response to step load

changes 4/ 7/

V_TLD

50% to/from 100% load

4, 5, 6

300

mV pk

Recovery time, step load

changes 4/ 7/ 8/

T_TLD

200

µS

Output response to step line

changes 4/ 6/ 9/

V_TLN

T_TLN

V_OS

Input step 18 V to/from

40 V I_OUT= 4.8 A

4, 5, 6

-300

300

200

500

mV pk

µS

Recovery time, step line

changes 4/ 1/ 9/

Input step 18 V to/from

40 V I_OUT= 4.8 A

Turn-On overshoot 4/ 10/

Turn-On Delay 4/ 10/

10% load, 100% load

T_DLY

1/ Parameter is tested as part of design characterization or after design changes. Thereafter, parameter shall be

guaranteed to the limits specified.

2/ Applicable to positive and negative outputs.

3/ Output load current must be distributed such that at least 20 percent of the total load current is being provided by one of the

outputs.

4/ Load current split equally between +V_OUTand –V_OUT

5/ Cross regulation is measured with 20 percent rated load on output under test while changing the load on the other output

from 20 percent to 80 percent of rated.

6/ Capacitance load may be any value from 0 to the maximum limit without compromising DC performance.

7/ Load step transition time  10 microseconds.

8/ Recovery time is measured from the initiation of the transient to where V_OUThas returned to within 1 percent of its steady

state value at 50 percent load.

9/ Input line step transition time  100 microseconds.

10/ Turn-on delay time from either a step application of input power or a logic low to logic high transition on the enable pin.

SIZE

STANDARD

5962-10224

MICROCIRCUIT DRAWING

REVISION LEVEL

SHEET

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

1...3 4 567 8 9...11

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