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5962-0324601V9A

更新时间： 2024-02-02 06:17:36

品牌	Logo	应用领域
爱特美尔 - ATMEL		微控制器和处理器外围集成电路微处理器时钟
页数	文件大小	规格书
42页	3365K
描述
Low-Voltage Rad-Hard 32-bit SPARC Embedded Processor

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5962-0324601V9A 技术参数

生命周期：	Active	包装说明：	DIE,
Reach Compliance Code：	compliant	ECCN代码：	3A001.A.2.C
HTS代码：	8542.31.00.01	风险等级：	5.71
地址总线宽度：	32	位大小：	32
边界扫描：	YES	最大时钟频率：	30.3 MHz
外部数据总线宽度：	32	格式：	FLOATING POINT
集成缓存：	NO	JESD-30 代码：	X-XUUC-N
低功率模式：	YES	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	UNSPECIFIED
封装代码：	DIE	封装形状：	UNSPECIFIED
封装形式：	UNCASED CHIP	认证状态：	Qualified
筛选级别：	MIL-PRF-38535 Class V	速度：	15 MHz
最大供电电压：	3.45 V	最小供电电压：	3.15 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	NO LEAD	端子位置：	UPPER
uPs/uCs/外围集成电路类型：	MICROPROCESSOR, RISC	Base Number Matches：	1

5962-0324601V9A 数据手册

TSC695FL

Product Description

Integer Unit

The IU is designed for highly dependable space and military applications, and includes

support for error detection. The RISC architecture makes the creation of a processor

that can execute instructions at a rate approaching one instruction per processor clock

possible.

To achieve that rate of execution, the IU employs a four-stage instruction pipeline that

permits parallel execution of multiple instructions.

•

Fetch - The processor outputs the instruction address to fetch the instruction.

Decode - The instruction is placed in the instruction register and is decoded. The

processor reads the operands from the register file and computes the next

instruction address.

•

Execute - The processor executes the instruction and saves the results in temporary

registers. Pending traps are prioritized and internal traps are taken during this stage.

Write - If no trap is taken, the processor writes the result to the destination register.

All four stages operate in parallel, working on up to four different instructions at a time. A

basic ’single-cycle’ instruction enters the pipeline and completes in four cycles.

By the time it reaches the write stage, three more instructions have entered and are

moving through the pipeline behind it. So, after the first four cycles, a single-cycle

instruction exits the pipeline and a single-cycle instruction enters the pipeline on every

cycle. Of course, a ’single-cycle’ instruction actually takes four cycles to complete, but

they are called single cycle because with this type of instruction the processor can com-

plete one instruction per cycle after the initial four-cycle delay.

Floating-point Unit

The FPU is designed to provide execution of single and double-precision floating-point

instructions concurrently with execution of integer instructions by the IU. The FPU is

compliant to the ANSI/IEEE-754 (1985) floating-point standard.

The FPU is designed for highly dependable space and military applications, and

includes support for concurrent error detection and testability.

The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and

write stages (F, D, E and W). The fetch unit captures instructions and their addresses

from the data and address busses. The decode unit contains logic to decode the float-

ing-point instruction opcodes. The execution unit handles all instruction execution. The

execution unit includes a floating-point queue (FP queue), which contains stored float-

ing-point operate (FPop) instructions under execution and their addresses. The

execution unit controls the load unit, the store unit, and the datapath unit. The FPU

depends upon the IU to access all addresses and control signals for memory access.

Floating-point loads and stores are executed in conjunction with the IU, which provides

addresses and control signals while the FPU supplies or stores the data. Instruction

fetch for integer and floating-point instructions is provided by the IU.

The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR

is a 32-bit status and control register. It keeps track of rounding modes, floating-point

trap types, queue status, condition codes, and various IEEE exception information. The

floating-point queue contains the floating-point instruction currently under execution,

along with its corresponding address.

4204C–AERO–05/05

1 2 3 456 7 8...42

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与5962-0324601V9A相关器件

型号	品牌	描述	获取价格	数据表
5962-0324601VXC	ATMEL	Low-Voltage Rad-Hard 32-bit SPARC Embedded Processor	获取价格
5962-0324901QZX	ACTEL	Video Amplifier, 1 Channel(s), 1 Func, Bipolar, CDSO14, CERAMIC, FP-14	获取价格
5962-0325001QXC	ATMEL	Field Programmable Gate Array, 2304 CLBs, 46000 Gates, 2304-Cell, CMOS, PQFP160, MQFP-160	获取价格
5962-0325001QXX	ACTEL	Field Programmable Gate Array, 40000 Gates, CMOS, CQFP160,	获取价格
5962-0325001QYC	ATMEL	Field Programmable Gate Array, 2304 CLBs, 46000 Gates, 2304-Cell, CMOS, PQFP256, MQFP-256	获取价格
5962-0325001VYC	ATMEL	Field Programmable Gate Array, 2304 CLBs, 46000 Gates, CMOS, PQFP256, MQFP-256	获取价格

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