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5962-01-392-1748 PDF预览

5962-01-392-1748

更新时间： 2024-01-01 10:04:21
品牌 Logo 应用领域
亚德诺 - ADI 信息通信管理转换器
页数 文件大小 规格书
14页 419K
描述
IC,A/D CONVERTER,SINGLE,12-BIT,BICMOS,DIP,28PIN

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5962-01-392-1748 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP28,.6针数：28
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.84
最大模拟输入电压：10 V转换器类型：A/D CONVERTER
JESD-30 代码：R-XDIP-T28最大线性误差 (EL)：0.024%
位数：12功能数量：1
端子数量：28最高工作温度：70 °C
最低工作温度：输出位码：OFFSET BINARY
封装主体材料：CERAMIC封装代码：DIP
封装等效代码：DIP28,.6封装形状：RECTANGULAR
封装形式：IN-LINE电源：5,+-12 V
认证状态：Not Qualified子类别：Analog to Digital Converters
表面贴装：NO技术：BICMOS
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

5962-01-392-1748 数据手册

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AD678  
PIN DESCRIPTION  
28-Pin DIP 44-Lead  
Symbol  
Pin No.  
JLCC Pin No. Type Name and Function  
AGND  
AIN  
BIPOFF  
7
6
10  
11  
10  
15  
P
AI  
AI  
Analog Ground. This is the ground return for AIN only.  
Analog Signal Input.  
Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight binary  
output coding. Connect to REFOUT through 50 Ω resistor for ±5 V input bipolar mode  
and twos complement binary output coding. See Figures 7 and 8.  
Chip Select. Active LOW.  
CS  
DGND  
DB11–DB4  
4
14  
26–19  
6
23  
DI  
P
Digital Ground  
40, 39, 37, 36, DO  
35, 34, 33, 31  
Data Bits 11 through 4. In 12-bit format (see 12/8 pin), these pins provide the upper 8 bits  
of data. In 8-bit format, these pins provide all 12 bits in two bytes (see R/L pin).  
Active HIGH.  
DB3, DB2  
18, 17  
16  
30, 27  
DO  
Data Bits 3 and 2. In 12-bit format, these pins provide Data Bit 3 and Data Bit 2.  
Active HIGH. In 8-bit format they are undefined and should be tied to VDD  
In 12-bit format, Data Bit 1. Active HIGH.  
.
DB1 (R/L)  
DB0 (HBE) 15  
EOC  
26  
25  
42  
DO  
DO  
DO  
In 12-bit format, Data Bit 0. Active HIGH.  
27  
End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the  
conversion is finished. In asynchronous mode, EOC is an open drain output and  
requires an external 3 kΩ pull-up resistor. See EOCEN and SYNC pins for information  
on EOC gating.  
EOCEN  
HBE (DB0) 15  
1
1
25  
DI  
DI  
End-Of-Convert Enable. Enables EOC pin. Active LOW.  
In 8-bit format, High Byte Enable. If LOW, output contains high byte. If HIGH, output  
contains low byte.  
OE  
2
3
DI  
Output Enable. The falling edge of OE enables DB11–DB0 in 12-bit format and  
DB11–DB4 in 8-bit format. Gated with CS. Active LOW.  
Reference Input. +5 V input gives 10 V full-scale range.  
+5 V Reference Output. Tied to REFIN through 50 Ω resistor for normal operation.  
In 8-bit format, Right/Left justified. Sets alignment of 12-bit result within 16-bit field.  
Tied to VDD for right-justified output and tied to DGND for left-justified output.  
Start Convert. Active LOW. See SYNC pin for gating.  
SYNC Control. If tied to VDD (synchronous mode), SC, EOC and EOCEN are gated  
by CS. If tied to DGND (asynchronous mode), SC and EOCEN are independent of CS,  
and EOC is an open drain output. EOC requires an external 3 kΩ pull-up resistor in  
asynchronous mode.  
REFIN  
REFOUT  
R/L (DB1)  
9
8
16  
14  
12  
26  
AI  
AO  
DI  
SC  
SYNC  
3
13  
5
21  
DI  
DI  
VCC  
VEE  
VDD  
12/8  
11  
5
28  
12  
17  
8
43  
19  
P
P
P
DI  
+12 V Analog Power.  
–12 V Analog Power.  
+5 V Digital Power.  
Twelve/eight-bit format. If tied HIGH, sets output format to 12-bit parallel. If tied  
LOW, sets output format to 8-bit multiplexed.  
No Connect  
—
2, 4, 7, 9, 13,  
16, 18, 20, 22,  
24, 28, 29, 32,  
38, 41, 44  
—
These pins are unused and should be connected to DGND or VDD.  
Type: AI = Analog Input; AO = Analog Output; DI = Digital Input (TTL and 5 V CMOS compatible); DO = Digital Output (TTL and 5 V CMOS compatible).  
All DO pins are three-state drivers; P = Power.  
PIN CONFIGURATIONS  
DIP PACKAGE  
JLCC PACKAGE  
–6–  
REV. B  
1...3456789...14

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