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5962-01-295-0960 PDF预览

5962-01-295-0960

更新时间: 2024-01-20 07:06:20
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
9页 90K
描述
FIFO, 64X4, Asynchronous, CMOS, CDIP16

5962-01-295-0960 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最大时钟频率 (fCLK):10 MHz
JESD-30 代码:R-XDIP-T16JESD-609代码:e0
内存集成电路类型:OTHER FIFO内存宽度:4
端子数量:16字数:64 words
字数代码:64工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:64X4封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
子类别:FIFOs最大压摆率:0.045 mA
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30Base Number Matches:1

5962-01-295-0960 数据手册

 浏览型号5962-01-295-0960的Datasheet PDF文件第3页浏览型号5962-01-295-0960的Datasheet PDF文件第4页浏览型号5962-01-295-0960的Datasheet PDF文件第5页浏览型号5962-01-295-0960的Datasheet PDF文件第7页浏览型号5962-01-295-0960的Datasheet PDF文件第8页浏览型号5962-01-295-0960的Datasheet PDF文件第9页 
IDT72401/72403  
CMOS PARALLEL FIFO 64 x 4, 64 x 5  
MILITARY AND COMMERCIAL  
TEMPERATURE RANGES  
(2)  
SO  
(3)  
(5)  
SI  
tIPH  
tPT  
(4)  
(1)  
IR  
tSIR  
tHIR  
INPUT DATA  
STABLE DATA  
2747 drw 08  
NOTES:  
1. FIFO is initially full.  
2. SO pulse is applied.  
3. SI is held HIGH.  
4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO.  
5. The write pointer is incremented. SI should not go LOW until (tPT + tIPH).  
Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH  
1/fOUT  
1/fOUT  
tSOH  
tSOL  
(2)  
SO  
OR  
tORH  
tORL  
tODS  
tODH  
(1)  
A-DATA  
B-DATA  
C-DATA  
OUTPUT DATA  
2747 drw 09  
NOTES:  
1. This data is loaded consecutively A, B, C.  
2. Data is shifted out when SO makes a HIGH to LOW transition.  
Figure 5. Output TIming  
SO(7)  
(2)  
(4)  
(1)  
(5)  
(3)  
OR  
(6)  
A or B  
OUTPUT DATA  
A- DATA  
B- DATA  
2747 drw 10  
NOTES:  
1. OR HIGH indicates that data is available and a SO pulse may be applied.  
2. SO goes HIGH causing the next step.  
3. OR goes LOW.  
4. The read pointer is incremented.  
5. OR goes HIGH indicating that new data (B) is now available at the FIFO outputs.  
6. If the FIFO has only one word loaded (A DATA) then OR stays LOW and the A DATA remains unchanged at the outputs.  
7. SO pulses applied when OR is LOW will be ignored.  
Figure 6. The Mechanism of Shifting Data Out of the FIFO  
6

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