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5962-0054001V9X

更新时间： 2024-01-25 02:30:25

品牌	Logo	应用领域
爱特美尔 - ATMEL		微控制器和处理器外围集成电路微处理器时钟
页数	文件大小	规格书
42页	2495K
描述
RISC Microprocessor, 32-Bit, 25MHz, CMOS, MQFP-256

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5962-0054001V9X 技术参数

生命周期：	Active	零件包装代码：	QFP
包装说明：	QFF,	针数：	256
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.31.00.01	风险等级：	5.79
地址总线宽度：	32	位大小：	32
边界扫描：	YES	最大时钟频率：	50 MHz
外部数据总线宽度：	32	格式：	FLOATING POINT
集成缓存：	NO	长度：	37.085 mm
低功率模式：	YES	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	UNSPECIFIED
封装代码：	QFF	封装形式：	FLATPACK
认证状态：	Qualified	筛选级别：	MIL-PRF-38535 Class V
座面最大高度：	3.18 mm	速度：	25 MHz
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	FLAT	端子节距：	0.508 mm
端子位置：	QUAD	宽度：	37.085 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR, RISC	Base Number Matches：	1

5962-0054001V9X 数据手册

TSC695F

Product Description

Integer Unit

The Integer Unit (IU) is designed for highly dependable space and military applications,

and includes support for error detection. The RISC architecture makes the creation of a

processor that can execute instructions at a rate approaching one instruction per pro-

cessor clock possible.

To achieve that rate of execution, the IU employs a four-stage instruction pipeline that

permits parallel execution of multiple instructions.

•

Fetch - The processor outputs the instruction address to fetch the instruction.

Decode - The instruction is placed in the instruction register and is decoded. The

processor reads the operands from the register file and computes the next

instruction address.

•

Execute - The processor executes the instruction and saves the results in temporary

registers. Pending traps are prioritized and internal traps are taken during this stage.

Write - If no trap is taken, the processor writes the result to the destination register.

All four stages operate in parallel, working on up to four different instructions at a time. A

basic ‘single-cycle’ instruction enters the pipeline and completes infour cycles.

By the time it reaches the write stage, three more instructions have entered and are

moving through the pipeline behind it. So, after the first four cycles, a single-cycle

instruction exits the pipeline and a single-cycle instruction enters the pipeline on every

cycle. Of course, a ’single-cycle’ instruction actually takes four cycles to complete, but

they are called single cycle because with this type of instruction the processor can com-

plete one instruction per cycle after the initial four-cycle delay.

Floating-point Unit

The FLoating Point Unit (FPU) is designed to provide execution of single and double-

precision floating-point instructions concurrently with execution of integer instructions by

the IU. The FPU is compliant to the ANSI/IEEE-754 (1985) floating-point standard.

The FPU is designed for highly dependable space and military applications, and

includes support for concurrent error detection and testability.

The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and

write stages (F, D, E and W). The fetch unit captures instructions and their addresses

from the data and address buses. The decode unit contains logic to decode the floating-

point instruction opcodes. The execution unit handles all instruction execution. The exe-

cution unit includes a floating-point queue (FP queue), which contains stored floating-

point operate (FPop) instructions under execution and their addresses. The execution

unit controls the load unit, the store unit, and the datapath unit. The FPU depends upon

the IU to access all addresses and control signals for memory access. Floating-point

loads and stores are executed in conjunction with the IU, which provides addresses and

control signals while the FPU supplies or stores the data. Instruction fetch for integer

and floating-point instructions is provided by the IU.

The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR

is a 32-bit status and control register. It keeps track of rounding modes, floating-point

trap types, queue status, condition codes, and various IEEE exception information. The

floating-point queue contains the floating-point instruction currently under execution,

along with its corresponding address.

4118H–AERO–06/03

1 2 3 456 7 8...42

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与5962-0054001V9X相关器件

型号	品牌	描述	获取价格	数据表
5962-0054001VXC	ATMEL	Rad-Hard 32-bit SPARC Embedded Processor	获取价格
5962-0054301QXC	ACTEL	Field Programmable Gate Array, 72000 Gates, 206MHz, 6036-Cell, CMOS, CQFP256, CERAMIC, QFP	获取价格
5962-00-547-6518	FAIRCHILD	D Latch, 2-Func, 4-Bit, TTL, CDIP24,	获取价格
5962-00-547-6808	FAIRCHILD	Decade Counter, Synchronous, Up Direction, TTL, CDIP16,	获取价格
5962-00-583-7993	FAIRCHILD	D Latch, 1-Func, 4-Bit, TTL, CDIP16,	获取价格
5962-00-610-3053	FAIRCHILD	Operational Amplifier, 1 Func, 6000uV Offset-Max, BIPolar, MBCY8,	获取价格

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