Datasheet > 5962-0051001QXA

5962-0051001QXA

更新时间： 2024-01-31 04:20:05

品牌	Logo	应用领域
德州仪器 - TI		外围集成电路时钟
页数	文件大小	规格书
81页	1213K
描述
FIXED POINT SIGNAL PROCESSOR

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5962-0051001QXA 技术参数

生命周期：	Active	零件包装代码：	BGA
包装说明：	BGA, BGA429,21X21,50	针数：	429
Reach Compliance Code：	not_compliant	ECCN代码：	3A001.A.2.C
HTS代码：	8542.31.00.01	风险等级：	5.26
其他特性：	ALSO REQUIRES 3.3V SUPPLY	地址总线宽度：	22
桶式移位器：	NO	位大小：	32
边界扫描：	YES	最大时钟频率：	200 MHz
外部数据总线宽度：	32	格式：	FIXED POINT
集成缓存：	YES	内部总线架构：	MULTIPLE
JESD-30 代码：	S-CBGA-B429	JESD-609代码：	e0
长度：	27 mm	低功率模式：	YES
DMA 通道数量：	4	外部中断装置数量：	4
端子数量：	429	计时器数量：	2
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	BGA
封装等效代码：	BGA429,21X21,50	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	1.5,3.3 V	认证状态：	Qualified
RAM（字数）：	131072	筛选级别：	MIL-PRF-38535
座面最大高度：	3.3 mm	子类别：	Digital Signal Processors
最大供电电压：	1.57 V	最小供电电压：	1.43 V
标称供电电压：	1.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	27 mm
uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER	Base Number Matches：	1

5962-0051001QXA 数据手册

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SGUS033 – FEBRUARY 2002

CPU (DSP core) description

The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight

32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture

features controls by which all eight units do not have to be supplied with instructions if they are not ready to

execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute

packet as the previous instruction, or whether it should be executed in the following clock as a part of the next

execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The

variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other

VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains

functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files

each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along

with two register files, compose sides A and B of the CPU [see the functional and CPU (DSP core) block diagram

and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to

that side. Additionally, each side features a single data bus connected to all the registers on the other side, by

which the two sets of functional units can access data from the register files on the opposite side. While register

access by functional units on the same side of the CPU as the register file can service all the units in a single

clock cycle, register access using the register file across the CPU supports one read and one write per cycle.

Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers

(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data

transfers between the register files and the memory. The data address driven by the .D units allows data

addresses generated from one register file to be used to load or store data to or from the other register file. The

C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes

with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some

registers, however, are singled out to support specific addressing or to hold the condition for conditional

instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.

The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results

available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.

The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least

significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous

execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,

effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the

256-bit-wide fetch-packet boundary, the assembler places it in the next fetch packet, while the remainder of the

current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can

vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per

clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch

packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units

for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit

registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store

instructions are byte-, half-word, or word-addressable.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

1...3 4 567 8 9...81

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5962-0051201Q2A	TI	FAMILY OF LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN	获取价格
5962-0051201QHA	TI	FAMILY OF LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN	获取价格
5962-0051201QPA	TI	FAMILY OF LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN	获取价格
5962-0051202Q2A	TI	FAMILY OF LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN	获取价格
5962-0051202QHA	TI	FAMILY OF LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN	获取价格

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