Si570/Si571
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Symbol
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
Typ
3.3
2.5
1.8
Max
3.63
2.75
1.89
Unit
Parameter
Supply Voltage1
VDD
V
Output enabled
LVPECL
CML
—
—
—
—
130
117
108
98
120
108
99
Supply Current
IDD
mA
LVDS
90
CMOS
TriState mode
—
0.75 x VDD
—
60
—
—
75
—
Output Enable (OE)2,
Serial Data (SDA),
Serial Clock (SCL)
VIH
VIL
V
0.5
Operating Temperature Range
TA
–40
—
85
ºC
Notes:
1. Selectable parameter specified by part number. See Section "7. Ordering Information" on page 31 for further details.
2. OE pin includes a 17 k pullup resistor to VDD. See “7.Ordering Information”.
Table 2. VC Control Voltage Input (Si571)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
33
45
90
Control Voltage Tuning Slope1,2,3
KV
VC 10 to 90% of VDD
—
—
ppm/V
135
180
356
BSL
–5
–10
9.3
500
—
±1
±5
+5
+10
10.7
—
Control Voltage Linearity4
LVC
%
Incremental
Modulation Bandwidth
VC Input Impedance
Nominal Control Voltage5
Control Voltage Tuning Range
Notes:
BW
ZVC
10.0
—
kHz
k
V
VCNOM
VC
@ fO
VDD/2
—
0
VDD
V
1. Positive slope; selectable option by part number. See "7. Ordering Information" on page 31.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope is
determined with VC ranging from 10 to 90% of VDD
.
5. Nominal output frequency set by VCNOM = 1/2 x VDD
.
4
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Rev. 1.6 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 15, 2021