Datasheet > 557G-07T

557G-07T

更新时间： 2024-02-14 17:54:11

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管逻辑集成电路
页数	文件大小	规格书
8页	113K
描述
Multiplexer, 557 Series, 1-Func, 2 Line Input, 1 Line Output, Complementary Output, PDSO16, 0.173 INCH, TSSOP-16

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557G-07T 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	16
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.71	系列：	557
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e0
长度：	5 mm	逻辑集成电路类型：	MULTIPLEXER
功能数量：	1	输入次数：	2
输出次数：	1	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	输出极性：	COMPLEMENTARY
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	225	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	4.4 mm
Base Number Matches：	1

557G-07T 数据手册

P R E L I M I N A R Y I N F O R M AT I O N

ICS557-07

2:1 Multiplexer Chip for PCI-E

Applications Information

External Components

Output Structures

6*IREF

A minimum number of external components are

required for proper operation.

IREF

=2.3 mA

Decoupling Capacitors

Decoupling capacitors of 0.01 µF should be connected

between VDD and the ground plane (pin 4) as close to

the VDD pin as possible. Do not share ground vias

between components. Route power from power source

through the capacitor pad and then into ICS pin.

Crystal

See Output Termination

Sections - Pages 3 ~ 5

A 25 MHz fundamental mode parallel resonant crystal

Ω

R_R475

with C = 16 pF should be used. This crystal must have

less than 300 ppm of error across temperature in order

for the ICS557-07 to meet PCI Express specifications.

General PCB Layout Recommendations

Crystal Capacitors

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

Crystal capacitors are connected from pins X1 to

ground and X2 to ground to optimize the accuracy of

the output frequency.

1. Each 0.01µF decoupling capacitor should be

mounted on the component side of the board as close

to the VDD pin as possible.

C = Crystal’s load capacitance in pF

Crystal Capacitors (pF) = (C - 8) * 2

For example, for a crystal with a 16 pF load cap, each

external crystal cap would be 16 pF. (16-8)*2=16.

2. No vias should be used between decoupling

capacitor and VDD pin.

Current Source (Iref) Reference Resistor - R_R

3. The PCB trace to VDD pin should be kept as short

as possible, as should the PCB trace to the ground via.

Distance of the ferrite bead and bulk decoupling from

the device is less critical.

If board target trace impedance (Z) is 50Ω, then R =

475Ω (1%), providing IREF of 2.32 mA. The output

current (I ) is equal to 6*IREF.

4. An optimum layout is one with all components on the

same side of the board, minimizing vias through other

signal layers (any ferrite beads and bulk decoupling

capacitors can be mounted on the back). Other signal

traces should be routed away from the ICS557-07.This

includes signal traces just underneath the device, or on

layers adjacent to the ground plane layer used by the

device.

Output Termination

The PCI-Express differential clock outputs of the

ICS557-07 are open source drivers and require an

external series resistor and a resistor to ground. These

resistor values and their allowable locations are shown

in detail in the PCI-Express Layout Guidelines

section.

The ICS557-07can also be configured for LVDS

compatible voltage levels. See the LVDS Compatible

Layout Guidelines section

MDS 557-07 B

Revision 041405

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

1 234 5 6 7 8

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