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54LS193 PDF预览

54LS193

更新时间: 2024-01-31 23:20:14
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器
页数 文件大小 规格书
9页 278K
描述
PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER

54LS193 技术参数

生命周期:Obsolete包装说明:QCCN, LCC20,.35SQ
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.23Is Samacsys:N
其他特性:TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK计数方向:BIDIRECTIONAL
系列:LSJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):15 pF
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:20000000 Hz最大I(ol):0.004 A
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:5 V
最大电源电流(ICC):34 mA传播延迟(tpd):54 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:1.905 mm子类别:Counters
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD触发器类型:POSITIVE EDGE
宽度:8.89 mm最小 fmax:25 MHz
Base Number Matches:1

54LS193 数据手册

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SN54/74LS192 SN54/74LS193  
FUNCTIONAL DESCRIPTION  
The LS192 and LS193 are Asynchronously Presettable  
Decade and 4-Bit Binary Synchronous UP/DOWN (Revers-  
able) Counters. The operating modes of the LS192 decade  
counter and the LS193 binary counter are identical, with the  
only difference being the count sequences as noted in the  
State Diagrams. Each circuit contains four master/slave  
flip-flops, with internal gating and steering logic to provide  
master reset, individual preset, count up and count down  
operations.  
Each flip-flop contains JK feedback from slave to master  
such that a LOW-to-HIGH transition on its T input causes the  
slave, and thus the Q output to change state. Synchronous  
switching, as opposed to ripple counting, is achieved by  
driving the steering gates of all stages from a common Count  
Up line and a common Count Down line, thereby causing all  
state changes to be initiated simultaneously. A LOW-to-HIGH  
transition on the Count Up input will advance the count by one;  
a similar transition on the Count Down input will decrease the  
count by one. While counting with one clock input, the other  
shouldbe held HIGH. Otherwise, the circuit will either count by  
twos or not at all, depending on the state of the first flip-flop,  
which cannot toggle as long as either Clock input is LOW.  
The Terminal Count Up (TC ) and Terminal Count Down  
U
(TC ) outputs are normally HIGH. When a circuit has reached  
D
the maximum count state (9 for the LS192, 15 for the LS193),  
the next HIGH-to-LOW transition of the Count Up Clock will  
cause TC to go LOW. TC will stay LOW until CP goes  
U
U
U
HIGH again, thus effectively repeating the Count Up Clock,  
but delayed by two gate delays. Similarly, the TC output will  
D
go LOW when the circuit is in the zero state and the Count  
Down Clock goes LOW. Since the TC outputs repeat the clock  
waveforms, they can be used as the clock input signals to the  
next higher order circuit in a multistage counter.  
Each circuit has an asynchronous parallel load capability  
permitting the counter to be preset. When the Parallel Load  
(PL) and the Master Reset (MR) inputs are LOW, information  
present on the Parallel Data inputs (P , P ) is loaded into the  
0
3
counter and appears on the outputs regardless of the  
conditions of the clock inputs. A HIGH signal on the Master  
Reset input will disable the preset gates, override both Clock  
inputs, and latch each Q output in the LOW state. If one of the  
Clock inputs is LOW during and after a reset or load operation,  
the next LOW-to-HIGH transition of that Clock will be  
interpreted as a legitimate signal and will be counted.  
MODE SELECT TABLE  
MR  
PL  
CP  
CP  
MODE  
U
D
H
L
L
L
L
X
L
H
H
H
X
X
H
X
X
H
H
Reset (Asyn.)  
Preset (Asyn.)  
No Change  
Count Up  
H
Count Down  
L = LOW Voltage Level  
H = HIGH Voltage Level  
X = Don’t Care  
= LOW-to-HIGH Clock Transition  
FAST AND LS TTL DATA  
5-354  

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