Datasheet > 54FCT374CTPYG

54FCT374CTPYG

更新时间： 2024-01-01 10:12:43

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
8页	212K
描述
Bus Driver/Transceiver

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

54FCT374CTPYG 技术参数

生命周期：	Active	Reach Compliance Code：	compliant
风险等级：	5.56	Base Number Matches：	1

54FCT374CTPYG 数据手册

IDT54/74FCT374T/AT/CT

FASTCMOSOCTALDREGISTER(3-STATE)

MILITARYANDINDUSTRIALTEMPERATURERANGES

TESTCIRCUITSANDWAVEFORMS

SWITCHPOSITION

7.0V

Test

Switch

Closed

Open

500W

Open Drain

Disable Low

Enable Low

OUT

Pulse

Generator

D.U.T

All Other Tests

50pF

500W

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Octal Link

Test Circuits for All Outputs

DATA

1.5V

INPUT

LOW-HIGH-LOW

tSU

1.5V

PULSE

1.5V

TIMING

INPUT

ASYNCHRONOUS CONTROL

tREM

PRESET

CLEAR

ETC.

1.5V

HIGH-LOW-HIGH

PULSE

1.5V

SYNCHRONOUS CONTROL

PRESET

1.5V

CLEAR

tSU

CLOCK ENABLE

ETC.

Pulse Width

Octal Link

Set-Up, Hold, and Release Times

ENABLE

DISABLE

1.5V

SAME PHASE

CONTROL

INPUT

1.5V

INPUT TRANSITION

PLH

PHL

PZL

tPLZ

VOH

OUTPUT

3.5V

1.5V

3.5V

1.5V

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

VOL

tPLH

0.3V

VOL

1.5V

tPZH

tPHZ

OPPOSITE PHASE

INPUT TRANSITION

VOH

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

1.5V

Octal Link

Propagation Delay

Enable and Disable Times

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

1...3 4 567 8

下载PDF

与54FCT374CTPYG相关器件

型号	品牌	描述	获取价格	数据表
54FCT374CTQG	IDT	Bus Driver/Transceiver	获取价格
54FCT374CTSOG	IDT	Bus Driver/Transceiver	获取价格
54FCT374D	NSC	Octal D-Type Flip-Flop with TRI-STATE Outputs	获取价格
54FCT374DB	IDT	CDIP-20, Tube	获取价格
54FCT374DM	IDT	D Flip-Flop, 8-Func, CMOS, CDIP20	获取价格
54FCT374DMQB	NSC	Octal D-Type Flip-Flop with TRI-STATE Outputs	获取价格