54F161A

更新时间： 2024-02-01 11:02:46

品牌	Logo	应用领域
德州仪器 - TI		计数器
页数	文件大小	规格书
12页	431K
描述
54F161A/54F163A Synchronous Presettable Binary Counter

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

54F161A 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	DIP, DIP16,.3
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.92	计数方向：	UP
JESD-30 代码：	R-XDIP-T16	JESD-609代码：	e0
负载/预设输入：	YES	逻辑集成电路类型：	BINARY COUNTER
工作模式：	SYNCHRONOUS	湿度敏感等级：	2A
功能数量：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC	封装代码：	DIP
封装等效代码：	DIP16,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	250
电源：	5 V	认证状态：	Not Qualified
子类别：	Counters	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	TTL
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
Base Number Matches：	1

54F161A 数据手册

Functional Description

The ’F161A and ’F163A count in modulo-16 binary se-

quence. From state 15 (HHHH) they increment to state 0

(LLLL). The clock inputs of all flip-flops are driven in parallel

through a clock buffer. Thus all changes of the Q outputs

(except due to Master Reset of the ’F161A) occur as a re-

sult of, and synchronous with, the LOW-to-HIGH transition

of the CP input signal. The circuits have four fundamental

modes of operation, in order of precedence: asynchronous

reset (’F161A), synchronous reset (’F163A), parallel load,

count-up and hold. Five control inputsÐMaster Reset (MR,

’F161A), Synchronous Reset (SR, ’F163A), Parallel Enable

(PE), Count Enable Parallel (CEP) and Count Enable Trickle

(CET)Ðdetermine the mode of operation, as shown in the

Mode Select Table. A LOW signal on MR overrides all other

inputs and asynchronously forces all outputs LOW. A LOW

signal on SR overrides counting and parallel loading and

allows all outputs to go LOW on the next rising edge of CP.

A LOW signal on PE overrides counting and allows informa-

flip-flops on the next rising edge of CP. With PE and MR

(’F161A) or SR (’F163A) HIGH, CEP and CET permit count-

ing when both are HIGH. Conversely, a LOW signal on ei-

ther CEP or CET inhibits counting.

The ’F161A and ’F163A use D-type edge triggered flip-flops

and changing the SR, PE, CEP and CET inputs when the CP

is in either state does not cause errors, provided that the

recommended setup and hold times, with respect to the ris-

ing edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is HIGH

and the counter is in state 15. To implement synchronous

multi-stage counters, the TC outputs can be used with the

CEP and CET inputs in two different ways. Please refer to

the ’F568 data sheet. The TC output is subject to decoding

spikes due to internal race conditions and is therefore not

recommended for use as a clock or asynchronous reset for

flip-flops, counters or registers.

Logic Equations: Count Enable

CEP CET PE

CET

tion on the Parallel Data (P ) inputs to be loaded into the

State Diagram

Mode Select Table

Action on the Rising

*SR

CET

CEP

Clock Edge (L)

Reset (Clear)

^{Load (P}_nxQ )

Count (Increment)

No Change (Hold)

*For ’F163A only

HIGH Voltage Level

LOW Voltage Level

Immaterial

TL/F/9486–5

Obsolete

1 2 345 6 7...12

下载PDF

与54F161A相关器件

型号	品牌	描述	获取价格	数据表
54F161A/B2A	ETC	Synchronous Up Counter	获取价格
54F161A/BEA	ETC	Synchronous Up Counter	获取价格
54F161A/BEAJC	MOTOROLA	F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERDIP-16	获取价格
54F161A/BFA	ETC	Synchronous Up Counter	获取价格
54F161A/BFAJC	MOTOROLA	F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDFP16, CERAMIC, FP-16	获取价格
54F161ADC	ETC	COUNTER\|UP\|4-BIT BINARY\|F-TTL\|DIP\|16PIN\|CERAMIC	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

54F161A

54F161A 技术参数

54F161A 数据手册

与54F161A相关器件

与54F161A相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

54F161A

54F161A 技术参数

54F161A 数据手册

与54F161A相关器件

与54F161A相关文章

您还可以找

您在本页遇到什么问题？