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54ACTQ374DMQB PDF预览

54ACTQ374DMQB

更新时间: 2024-02-20 19:13:49
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
8页 22K
描述
FLIP-FLOP|OCTAL|D TYPE|ACT-CMOS|DIP|20PIN|CERAMIC

54ACTQ374DMQB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DFP, FL20,.3Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.16
Is Samacsys:N系列:ACT
JESD-30 代码:R-GDFP-F20JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:95000000 Hz最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装等效代码:FL20,.3
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):1.6 mA传播延迟(tpd):11.5 ns
认证状态:Not Qualified筛选级别:MIL-PRF-38535 Class V
座面最大高度:2.286 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn63Pb37)端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40总剂量:100k Rad(Si) V
触发器类型:POSITIVE EDGE宽度:6.731 mm
Base Number Matches:1

54ACTQ374DMQB 数据手册

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MICROCIRCUIT DATA SHEET  
MN54ACTQ374-X REV 2A0  
Electrical Characteristics  
AC PARAMETERS  
(The following conditions apply to all the following parameters, unless otherwise specified.)  
AC: CL=50pF, RL=500 OHMS, TR=3.0ns, TF=3.0ns, Temp range: -55C to +125C. NOTE: -55C TEMPERATURE, SUBGROUP  
11 IS GUARANTEED BUT NOT TESTED.  
PIN-  
NAME  
SUB-  
SYMBOL  
tpLH  
PARAMETER  
CONDITIONS  
NOTES  
MIN  
1.5  
MAX UNIT  
9.5  
GROUPS  
Propagation Delay VCC=4.5V  
3,  
CP to  
4, 7 On  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
9
3,  
CP to  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
3.5  
2.0  
5.0  
11.5  
9.5  
10, 11  
4, 7 On  
tpHL  
tpZH  
tpZL  
tpHZ  
tpLZ  
Propagation Delay VCC=4.5V  
3,  
4, 7 On  
CP to  
9
3,  
4, 7 On  
CP to  
11.5  
9.5  
10, 11  
Output Enable  
Time  
VCC=4.5V  
VCC=4.5V  
VCC=4.5V  
VCC=4.5V  
VCC=4.5V  
3,  
4, 7 On  
OE to  
9
3,  
4, 7 On  
OE to  
11.5  
9.5  
10, 11  
9
Output Enable  
Time  
3,  
4, 7 On  
OE to  
3,  
4, 7 On  
OE to  
11.5  
9.5  
10, 11  
9
Output Disable  
Time  
3,  
4, 7 On  
OE to  
3,  
4, 7 On  
OE to  
10.5  
9.5  
10, 11  
9
Output Disable  
Time  
3,  
4, 7 On  
OE to  
3,  
4, 7 On  
OE to  
10.5  
10, 11  
ts(H/L)  
th(H/L)  
tw(H/L)  
Setup Time HIGH  
or LOW  
6
6
6
Dn to  
CP  
9, 10,  
11  
Hold Time HIGH or VCC=4.5V  
LOW  
Dn to  
CP  
9, 10,  
11  
Pulse Width  
VCC=4.5V  
CP  
Pulse  
Width  
9, 10,  
11  
Fmax  
Maximum Clock  
Frequency  
VCC=4.5V  
6
95  
MHz 9, 10,  
11  
Note 1: SCREEN TESTED 100% ON EACH DEVICE AT +25C & +125C TEMPERATURE, SUBGROUPS 1, 2, 7, &  
8.  
Note 2: SAMPLE TESTED (METHOD 5005, TABLE 1) ON EACH MFG. LOT AT +25C & +125C TEMPERATURE,  
SUBGROUPS A1, 2, 7, & 8.  
Note 3: SCREEN TESTED 100% ON EACH DEVICE AT +25C TEMPERATURE ONLY, SUBGROUP A9.  
Note 4: SAMPLE TESTED (METHOD 5005, TABLE 1) ON EACH MFG. LOT AT +25C & +125C TEMPERATURE,  
SUBGROUPS A9 & 10.  
Note 5: TRANSMISSION LINE DRIVING TEST, GUARDBAND LIMITS SET FOR +25C, 2 MSEC DURATION MAX.  
Note 6: DESIGN CHARACTERIZATION DATA ONLY.  
Note 7: +25C & +125C MIN LIMITS GUARANTEED FOR 5.5V BY GUARDBANDING 4.5V MIN. LIMITS.  
6

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