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54ACT74DM PDF预览

54ACT74DM

更新时间: 2024-02-09 19:19:12
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 180K
描述
ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14

54ACT74DM 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.58系列:ACT
JESD-30 代码:R-GDIP-T14长度:19.43 mm
逻辑集成电路类型:D FLIP-FLOP位数:1
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):14 ns
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:85 MHz
Base Number Matches:1

54ACT74DM 数据手册

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AC Electrical Characteristics  
54ACT  
VCC  
(V)  
TA = −55˚C  
to +125˚C  
CL = 50 pF  
Fig.  
No.  
Symbol  
Parameter  
Units  
(Note 10)  
Min  
Max  
fmax  
Maximum Clock  
5.0  
5.0  
5.0  
5.0  
5.0  
85  
MHz  
ns  
Frequency  
tPLH  
tPHL  
tPLH  
tPHL  
Propagation Delay  
CDn or SDn to Qn or Qn  
Propagation Delay  
CDn or SDn to Qn or Qn  
Propagation Delay  
CPn to Qn or Qn  
1.0  
1.0  
1.0  
1.0  
11.5  
12.5  
14.0  
12.0  
ns  
ns  
Propagation Delay  
CPn to Qn or Qn  
ns  
Note 10: Voltage Range 5.0 is 5.0V 0.5V  
AC Operating Requirements  
54ACT  
TA = −55˚C  
CL = 50 pF  
Guaranteed  
Limits  
Symbol  
Parameter  
VCC  
Units  
Fig.  
No.  
(V)  
(Note 11)  
ts  
Set-up Time, HIGH or  
LOW  
5.0  
5.0  
4.0  
ns  
ns  
Dn to CPn  
th  
Hold Time, HIGH or  
LOW  
1.0  
Dn to CPn  
tw  
CPn or CDn or SDn  
Pulse Width  
5.0  
5.0  
7.0  
0.5  
ns  
ns  
trec  
Recovery Time  
CDn or SDn to CP  
Note 11: Voltage Range 5.0 is 5.0V 0.5V  
Capacitance  
Symbol  
Parameter  
Typ  
Units  
pF  
Conditions  
VCC = OPEN  
VCC = 5.0V  
CIN  
Input Capacitance  
Power Dissipation  
Capacitance  
4.5  
CPD  
35.0  
pF  
www.national.com  
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