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54ACQ373 PDF预览

54ACQ373

更新时间: 2024-01-26 00:00:34
品牌 Logo 应用领域
美国国家半导体 - NSC 锁存器
页数 文件大小 规格书
8页 173K
描述
Quiet Series Octal Transparent Latch with TRI-STATE Outputs

54ACQ373 技术参数

生命周期:Obsolete包装说明:QCCN,
Reach Compliance Code:unknown风险等级:5.84
系列:ACJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):16 ns
认证状态:Not Qualified筛选级别:MIL-STD-883
座面最大高度:1.905 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
宽度:8.89 mm

54ACQ373 数据手册

 浏览型号54ACQ373的Datasheet PDF文件第1页浏览型号54ACQ373的Datasheet PDF文件第3页浏览型号54ACQ373的Datasheet PDF文件第4页浏览型号54ACQ373的Datasheet PDF文件第5页浏览型号54ACQ373的Datasheet PDF文件第6页浏览型号54ACQ373的Datasheet PDF文件第7页 
Connection Diagrams  
Pin Assignment for  
DIP and Flatpak  
Pin Assignment  
for LCC  
DS100238-4  
DS100238-3  
Functional Description  
Truth Table  
The ’ACQ/’ACTQ373 contains eight D-type latches with  
TRI-STATE standard outputs. When the Latch Enable (LE)  
input is HIGH, data on the Dn inputs enters the latches. In  
this condition the latches are transparent, i.e., a latch output  
will change state each time its D input changes. When LE is  
LOW, the latches store the information that was present on  
the D inputs a setup time preceding the HIGH-to-LOW tran-  
sition of LE. The TRI-STATE standard outputs are controlled  
by the Output Enable (OE) input. When OE is LOW, the stan-  
dard outputs are in the 2-state mode. When OE is HIGH, the  
standard outputs are in the high impedance mode but this  
does not interfere with entering new data into the latches.  
Inputs  
Outputs  
LE  
X
OE  
H
L
Dn  
On  
Z
X
L
H
H
L
L
L
H
X
H
L
O0  
=
=
=
=
H
L
Z
X
O
HIGH Voltage Level  
LOW Voltage Level  
High Impedance  
Immaterial  
=
Previous O before HIGH to Low transition of Latch Enable  
0
0
Logic Diagram  
DS100238-5  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
www.national.com  
2

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