54AC11238

更新时间： 2024-01-19 20:18:32

品牌	Logo	应用领域
德州仪器 - TI		解码器解复用器
页数	文件大小	规格书
9页	116K
描述
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

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技术参数
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54AC11238 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	DIP, DIP16,.3
针数：	16	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.92	其他特性：	3 ENABLE INPUTS; CENTER VCC/GND PINS
系列：	AC	JESD-30 代码：	R-GDIP-T16
长度：	19.56 mm	负载电容（CL）：	50 pF
逻辑集成电路类型：	OTHER DECODER/DRIVER	最大I（ol）：	0.024 A
功能数量：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出极性：	TRUE	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装等效代码：	DIP16,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3/5 V
Prop。Delay @ Nom-Sup：	11.8 ns	传播延迟（tpd）：	10.9 ns
认证状态：	Not Qualified	座面最大高度：	5.08 mm
子类别：	Decoder/Drivers	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

54AC11238 数据手册

54AC11238, 74AC11238

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCAS039A – APRIL 1988 – REVISED APRIL 1993

54AC11238 . . . J PACKAGE

74AC11238 . . . D OR N PACKAGE

• Designed Specifically for High-Speed

Memory Decoders and Data Transmission

Systems

(TOP VIEW)

• Noninverting Version of ′AC11138

• Incorporates 3 Enable Inputs to Simplify

Cascading and/or Data Reception

• Flow-Through Architecture Optimizes

GND

PCB Layout

• Center-Pin V

and GND Configurations

Minimize High-Speed Switching Noise

G2A

G2B

• EPIC (Enhanced-Performance Implanted

CMOS) 1- m Process

• 500-mA Typical Latch-Up Immunity

at 125°C

54AC11238 . . . FK PACKAGE

(TOP VIEW)

• Package Options Include Plastic

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

20 19

G2A

17 G2B

description

The ′AC11238 circuit is designed to be

used in high-performance memory-decoding or

data-routing applications requiring very short

propagation delay times. In high-performance

memory systems, this decoder can be used to

minimize the effects of system decoding. When

employed with high-speed memories utilizing a

fast enable circuit, the delay times of this decoder

9 10 11 12 13

NC – No internal connection

and the enable time of the memory are usually less than the typical access time of the memory. This means that

the effective system delay introduced by the decoder is negligible.

The conditions at the binary select inputs and the three enable inputs select one of eight input lines. Two

active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.

A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one

inverter. An enable input can be used as a data input for demultiplexing applications.

The 54AC11238 is characterized for operation over the full military temperature range of – 55°C to 125°C. The

74AC11238 is characterized for operation from – 40°C to 85°C.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily

include testing of all parameters.

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

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与54AC11238相关器件

型号	品牌	描述	获取价格	数据表
54AC11238FK	ETC	3-To-8-Line Demultiplexer	获取价格
54AC11238J	ETC	3-To-8-Line Demultiplexer	获取价格
54AC11239FK	ETC	2-To-4-Line Demultiplexer	获取价格
54AC11239J	ETC	2-To-4-Line Demultiplexer	获取价格
54AC11240	TI	OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS	获取价格
54AC11240FK	ETC	Dual 4-Bit Inverting Buffer/Driver	获取价格

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