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54ABT373CMTCMQB PDF预览

54ABT373CMTCMQB

更新时间： 2024-01-16 20:45:07
品牌 Logo 应用领域
美国国家半导体 - NSC 锁存器
页数 文件大小 规格书
16页 331K
描述
Octal Transparent Latch with TRI-STATE Outputs

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54ABT373CMTCMQB 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：DFP, FL20,.3Reach Compliance Code：unknown
风险等级：5.81JESD-30 代码：R-XDFP-F20
JESD-609代码：e0负载电容（CL）：50 pF
逻辑集成电路类型：D LATCH最大I（ol）：0.048 A
位数：8功能数量：1
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
封装主体材料：CERAMIC封装代码：DFP
封装等效代码：FL20,.3封装形状：RECTANGULAR
封装形式：FLATPACK电源：5 V
Prop。Delay @ Nom-Sup：7 ns认证状态：Not Qualified
筛选级别：38535Q/M;38534H;883B子类别：FF/Latches
标称供电电压 (Vsup)：5 V表面贴装：YES
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：FLAT端子节距：1.27 mm
端子位置：DUALBase Number Matches：1

54ABT373CMTCMQB 数据手册

 浏览型号54ABT373CMTCMQB的Datasheet PDF文件第2页浏览型号54ABT373CMTCMQB的Datasheet PDF文件第3页浏览型号54ABT373CMTCMQB的Datasheet PDF文件第4页浏览型号54ABT373CMTCMQB的Datasheet PDF文件第6页浏览型号54ABT373CMTCMQB的Datasheet PDF文件第7页浏览型号54ABT373CMTCMQB的Datasheet PDF文件第8页 
Extended AC Electrical Characteristics  
(SOIC package)  
74ABT  
74ABT  
74ABT  
e b  
a
40 C to 85 C  
e b a  
40 C to 85 C  
T
T
§
4.5V to 5.5V  
§
§
4.5V to 5.5V  
§
A
A
e b  
a
40 C to 85 C  
T
§
§
4.5V to 5.5V  
A
e
e
V
V
CC  
CC  
e
V
CC  
e
e
250 pF  
Symbol  
Parameter  
C
50 pF  
C
L
Units  
L
e
C
250 pF  
(Note 5)  
L
8 Outputs Switching  
(Note 4)  
8 Outputs Switching  
(Note 6)  
Min  
Max  
Min  
Max  
Min  
Max  
t
t
Propagation Delay  
1.5  
1.5  
5.2  
5.2  
2.0  
2.0  
6.8  
6.8  
2.0  
2.0  
9.0  
9.0  
PLH  
ns  
ns  
ns  
ns  
D
n
to O  
n
PHL  
t
t
Propagation Delay  
LE to O  
1.5  
1.5  
5.5  
5.5  
2.0  
2.0  
7.5  
7.5  
2.0  
2.0  
9.5  
9.5  
PLH  
PHL  
n
t
t
Output Enable Time  
1.5  
1.5  
6.2  
6.2  
2.0  
2.0  
8.0  
8.0  
2.0  
2.0  
10.5  
10.5  
PZH  
PZL  
t
t
Output Disable Time  
1.0  
1.0  
5.5  
5.5  
PHZ  
(Note 7)  
(Note 7)  
PZL  
Note 4: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH,  
HIGH-to-LOW, etc.).  
Note 5: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in plce of the 50 pF load capacitors in  
the standard AC load. This specificaiton pertains to single output switching only.  
Note 6: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH,  
HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.  
Note 7: The TRI-STATE delay times are dominated by the RC network (500X, 250 pF) on the output and has been excluded from the datasheet.  
Skew  
74ABT  
74ABT  
e b  
a
40 C to 85 C  
e b  
A
a
40 C to 85 C  
T
T
§
4.5V–5.5V  
§
§
4.5V–5.5V  
§
A
e
e
V
CC  
V
CC  
C
Symbol  
Parameter  
e
e
250 pF  
Units  
C
50 pF  
L
L
8 Outputs Switching  
(Note 3)  
8 Outputs Switching  
(Note 4)  
Max  
Max  
t
Pin to Pin Skew  
HL Transitions  
OSHL  
(Note 1)  
1.0  
1.5  
ns  
ns  
ns  
ns  
ns  
t
Pin to Pin Skew  
LH Transitions  
OSLH  
(Note 1)  
1.0  
1.4  
1.5  
2.0  
1.5  
3.5  
3.9  
4.0  
t
Duty Cycle  
PS  
(Note 5)  
LH–HL Skew  
t
Pin to Pin Skew  
OST  
(Note 1)  
LH/HL Transitions  
t
Device to Device Skew  
LH/HL Transitions  
PV  
(Note 2)  
Note 1: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The  
specification applies to any outputs switching HIGH to LOW (t ), LOW to HIGH (t ), or any combination switching LOW to HIGH and/or HIGH to LOW  
OSHL OSLH  
(t  
OST  
). This specification is guaranteed but not tested.  
Note 2: Propagation delay variation for a given set of conditions (i.e., temperature and V ) from device to device. This specification is guaranteed but not tested.  
CC  
Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH,  
HIGH-to-LOW, etc.).  
Note 4: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in  
the standard AC load.  
Note 5: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the  
outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.  
5
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