Si550
Table 4. CLK± Output Levels and Symmetry (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Symmetry (duty cycle)
SYM
LVPECL:
LVDS:
CMOS:
V
– 1.3 V (diff)
DD
45
—
55
%
1.25 V (diff)
/2
V
DD
Notes:
1. 50 Ω to VDD – 2.0 V.
2. Rterm = 100 Ω (differential).
3. CL = 15 pF
Table 5. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Kv = 45 ppm/V
Min
Typ
Max
Units
1,2,3
Phase Jitter (RMS)
for F > 500 MHz
φJ
ps
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.35
0.38
—
—
OUT
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.43
0.41
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.52
0.46
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.64
0.52
—
—
1,2,3
Phase Jitter (RMS)
for F of 125 to 500 MHz
φJ
Kv = 45 ppm/V
ps
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.42
0.58
—
—
OUT
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.48
0.60
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.57
0.64
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.67
0.68
—
—
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4
Preliminary Rev. 0.3