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530BB62M5000DG PDF预览

530BB62M5000DG

更新时间： 2024-02-01 11:50:53
品牌 Logo 应用领域
芯科 - SILICON 石英晶振
页数 文件大小 规格书
12页 453K
描述
XO, Clock, 10MHz Min, 945MHz Max, 62.5MHz Nom

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530BB62M5000DG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：ActiveReach Compliance Code：compliant
风险等级：5.67JESD-609代码：e3
安装特点：SURFACE MOUNT端子数量：6
最大工作频率：945 MHz最小工作频率：10 MHz
标称工作频率：62.5 MHz最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装等效代码：DILCC6,.2电源：3.3 V
认证状态：Not Qualified子类别：Other Oscillators
最大压摆率：98 mA标称供电电压：3.3 V
表面贴装：YES端子面层：Matte Tin (Sn)
Base Number Matches：1

530BB62M5000DG 数据手册

 浏览型号530BB62M5000DG的Datasheet PDF文件第6页浏览型号530BB62M5000DG的Datasheet PDF文件第7页浏览型号530BB62M5000DG的Datasheet PDF文件第8页浏览型号530BB62M5000DG的Datasheet PDF文件第9页浏览型号530BB62M5000DG的Datasheet PDF文件第10页浏览型号530BB62M5000DG的Datasheet PDF文件第12页 
Si530/531  
Revision 1.1 to Revision 1.2  
DOCUMENT CHANGE LIST  
Revision 0.4 to Revision 0.5  
Updated 2.5 V/3.3 V and 1.8 V CML output level  
specifications for Table 3 on page 3.  
Updated Table 1, “Recommended Operating  
Added footnotes clarifying max offset frequency test  
Conditions,” on page 2.  
conditions for Table 4 on page 4.  
Added maximum supply current specifications.  
Specified relationship between temperature at startup  
and operation temperature.  
Added CMOS phase jitter specs to Table 4 on  
page 4.  
Removed the words "Differential Modes:  
LVPECL/LVDS/CML" in the footnote referring to  
AN256 in Table 4 on page 4.  
Updated Table 4, “CLK± Output Phase Jitter,” on  
page 4 to include maximum rms jitter generation  
specifications and updated typical rms jitter  
specifications.  
Separated 1.8 V, 2.5 V/3.3 V supply voltage  
specifications in Table 9 on page 5.  
Added Table 6, “CLK± Output Phase Noise  
Updated and clarified Table 9 on page 5 to include  
the "Moisture Sensitivity Level" and "Contact Pads"  
rows.  
(Typical),” on page 4.  
Added Output Enable active polarity as an option in  
Figure 1, “Part Number Convention,” on page 7.  
Updated Figure 3 on page 9 and Table 13 on page 9  
to reflect specific marking information. Previously,  
Figure 3 was generic.  
Revision 0.5 to Revision 1.0  
Updated Note 3 in Table 1, “Recommended  
Operating Conditions,” on page 2.  
Revision 1.2 to Revision 1.3  
Updated Figure 1, “Part Number Convention,” on  
Added Table 8, “Thermal Characteristics,” on  
page 7.  
page 5.  
Revision 1.0 to Revision 1.1  
Revision 1.3 to Revision 1.4  
Updated Table 1, “Recommended Operating  
Revised Figure 2 and Table 12 on page 8 to reflect  
Conditions,” on page 2.  
Device maintains stable operation over –40 to +85 ºC  
operating temperature range.  
current package outline diagram.  
Revised Figure 4 and Table 14 on page 10 to reflect  
the recommended PCB land pattern.  
Supply current specifications updated for revision D.  
Updated Table 2, “CLK± Output Frequency  
Revision 1.4 to Revision 1.5  
Characteristics,” on page 2.  
Added specification for ±20 ppm lifetime stability  
Changed “Trays” to “Coil Tape” in Ordering Guide.  
(±7 ppm temperature stability) XO.  
Updated Table 3, “CLK± Output Levels and  
Symmetry,” on page 3.  
Updated LVDS differential peak-peak swing  
specifications.  
Updated Table 4, “CLK± Output Phase Jitter,” on  
page 4.  
Updated Table 5, “CLK± Output Period Jitter,” on  
page 4.  
Revised period jitter specifications.  
1
Updated Table 9, “Absolute Maximum Ratings ,” on  
page 5 to reflect the soldering temperature time at  
260 ºC is 20–40 sec per JEDEC J-STD-020C.  
Updated 3. "Ordering Information" on page 7.  
Changed ordering instructions to revision D.  
Added 5. "Si530/Si531 Mark Specification" on page  
9.  
11  
Rev. 1.5  
1...89101112

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