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4282 PDF预览

4282

更新时间: 2024-01-24 04:37:47
品牌 Logo 应用领域
瑞萨 - RENESAS 计算机
页数 文件大小 规格书
69页 607K
描述
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4282 数据手册

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4282 Group  
REJ03B0084-0133Z  
Rev.1.33  
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER  
2004.03.18  
• Timer  
DESCRIPTION  
Timer 1 ................................................................... 8-bit timer  
(This has a reload register and carrier wave output auto-control  
function)  
Timer 2 ................................................................... 8-bit timer  
(This has two reload registers and carrier wave output function)  
• Logic operation function (XOR, OR, AND)  
• RAM back-up function  
The 4282 Group enables fabrication of 8 × 7 key matrix and has  
the followin timers;  
• an 8-bit timer which can be used to set each carrier wave and  
has two reload register  
• an 8-bit timer which can be used to auto-control and has a  
reload register.  
• Key-on wakeup function (ports D4–D7, E0–E2, G0–G3) .... 11  
• I/O port (ports D, E, G, CARR) .......................................... 16  
• Oscillation circuit ..................................... Ceramic resonance  
• Watchdog timer  
FEATURES  
• Number of basic instructions ............................................. 68  
• Minimum instruction execution time ............................ 8.0 µs  
(at f(XIN) = 4.0 MHz, system clock = f(XIN)/8)  
• Power-on reset circuit  
• Voltage drop detection circuit ......................... Typical:1.50 V  
(system reset)  
• Supply voltage ................................................. 1.8 V to 3.6 V  
• Subroutine nesting ..................................................... 4 levels  
APPLICATION  
Various remote control transmitters  
ROM (PROM) size  
RAM size  
Part number  
Package  
ROM type  
(× 9 bits)  
(× 4 bits)  
48 words  
64 words  
64 words  
M34282M1-XXXGP  
M34282M2-XXXGP  
M34282E2GP  
1024 words  
2048 words  
2048 words  
20P2E/F-A  
20P2E/F-A  
20P2E/F-A  
Mask ROM  
Mask ROM  
One Time PROM  
PIN CONFIGURATION (TOP VIEW)  
V
SS  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VDD  
CARR  
E
2
3
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
E
1
4
X
IN  
5
X
OUT  
6
E
G
G
0
0
1
7
8
9
G
2
10  
G
3
Outline 20P2E/F-A  
Rev.1.33 Mar 18, 2004 page 1 of 67  

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