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4235-01 PDF预览

4235-01

更新时间: 2024-01-04 02:28:41
品牌 Logo 应用领域
PSEMI 开关射频微波光电二极管
页数 文件大小 规格书
8页 288K
描述
SPDT UltraCMOS? RF Switch DC - 4000 MHz

4235-01 技术参数

生命周期:ObsoleteReach Compliance Code:compliant
风险等级:5.84Is Samacsys:N
射频/微波设备类型:SPDTBase Number Matches:1

4235-01 数据手册

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PE4235  
Product Specification  
Figure 3. Pin Configuration  
Table 4. Absolute Maximum Ratings  
Symbol Parameter/Conditions  
Min  
Max  
Units  
RF2  
GND  
RF1  
1
2
3
6
5
4
RFC  
CTRL  
VDD  
VDD  
Power Supply Voltage  
-0.3  
4.0  
V
Voltage on any input  
except for CTRL pin  
VI  
-0.3 VDD + 0.3  
V
Exposed Solder  
Pad - Shorted  
to Pin 2  
VCTRL  
TST  
Voltage on CTRL pin  
5
V
(bottom side)  
Storage temperature range  
-65  
-40  
150  
85  
°C  
Operating temperature  
range  
TOP  
PIN  
°C  
dBm  
V
Input power (50 )  
ESD Voltage (Human Body  
Model)  
19  
VESD  
200  
Table 2. Pin Descriptions  
Absolute Maximum Ratings are those values  
listed in the above table. Exceeding these values  
may cause permanent device damage.  
Pin  
No.  
Pin  
Name  
Description  
1
RF2  
RF2 port.1  
Functional operation should be restricted to the  
limits in the DC Electrical Specifications table.  
Exposure to absolute maximum ratings for  
extended periods may affect device reliability.  
2
GND  
Ground Connection. Traces should be  
physically short and connected to the  
ground plane. This pin is connected to  
the exposed solder pad that also must  
be soldered to the ground plane for best  
performance.  
3
4
RF1  
VDD  
RF1 port.1  
Control Logic Input  
Nominal 3 V supply connection.  
The control logic input pin (CTRL) is typically  
driven by a 3-volt CMOS logic level signal. For  
flexibility to support systems that have 5-volt  
control logic drivers, the control logic input has  
been designed to handle a standard 5-volt TTL  
control signal. This TTL control signal input must  
not exceed 5-volts or damage to the switch could  
result.  
5
CTRL  
CMOS or TTL logic level:  
High = RFC to RF1 signal path  
Low = RFC to RF2 signal path  
Common RF port for switch.1  
6
RFC  
Notes: 1. All RF pins must be DC blocked with an external series  
capacitor or held at 0 VDC  
.
Table 5. Control Logic Truth Table  
Table 3. DC Electrical Specifications  
Control Voltage  
Signal Path  
Parameter  
Min  
Typ  
Max  
Units  
CTRL = CMOS or TTL High  
CTRL = CMOS or TTL Low  
RFC to RF1  
RFC to RF2  
VDD Power Supply Voltage  
IDD Power Supply Current  
(VDD = 3V, VCNTL = 3V)  
Control Voltage High  
2.7  
3.0  
3.3  
V
250  
500  
nA  
Electrostatic Discharge (ESD) Precautions  
0.7xVDD  
V
V
When handling this UltraCMOS™ device, observe  
the same precautions that you would use with  
other ESD-sensitive devices. Although this device  
contains circuitry to protect it from damage due to  
ESD, precautions should be taken to avoid  
exceeding the rating specified in Table 4.  
Control Voltage Low  
0.3xVDD  
Latch-Up Avoidance  
Unlike conventional CMOS devices, UltraCMOS™  
devices are immune to latch-up.  
©2005 Peregrine Semiconductor Corp. All rights reserved.  
Document No. 70-0069-03 UltraCMOS™ RFIC Solutions  
Page 2 of 8  

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