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3D3521Z PDF预览

3D3521Z

更新时间: 2024-02-04 10:32:55
品牌 Logo 应用领域
DATADELAY 网络接口电信集成电路电信电路光电二极管编码器
页数 文件大小 规格书
4页 231K
描述
MONOLITHIC MANCHESTER ENCODER

3D3521Z 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.76Is Samacsys:N
JESD-30 代码:R-PDSO-G8长度:4.88 mm
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.73 mm标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:MANCHESTER ENCODER温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.91 mmBase Number Matches:1

3D3521Z 数据手册

 浏览型号3D3521Z的Datasheet PDF文件第1页浏览型号3D3521Z的Datasheet PDF文件第3页浏览型号3D3521Z的Datasheet PDF文件第4页 
3D3521  
APPLICATION NOTES  
The 3D3521 Manchester Encoder samples the  
data input at the rising edge of the input clock.  
The sampled data is used in conjunction with the  
clock rising and falling edges to generate the by-  
phase level Manchester code.  
OUTPUT SIGNAL CHARACTERISTICS  
The 3D3521 presents at its outputs the true and  
the complimented encoded data.  
The High-to-Low time skew of the selected data  
output should be budgeted by the user, as it  
relates to his application, to satisfactorily  
estimate the distortion of the transmitted data  
stream.  
INPUT SIGNAL CHARACTERISTICS  
The 3D3521 Manchester Encoder inputs are  
CMOS compatible. The user should assure  
himself that the 50% (of VDD) threshold is used  
when referring to all timing, especially to the input  
clock duty cycle.  
Such an estimate is very useful in determining  
the  
functionality and margins of the data link, if a  
3D3522 Manchester Decoder is used to decode  
the received data.  
CLOCK DUTY CYCLE ERRORS  
The 3D3521 Manchester Encoder employs the  
timing of the clock rising and falling edges (duty  
cycle) to implement the required coding scheme.  
To reduce the difference between the output data  
high time and low time, it is essential that the  
deviation of the input clock duty cycle from 50/50  
be minimized.  
POWER SUPPLY AND  
TEMPERATURE CONSIDERATIONS  
CMOS integrated circuitry is strongly dependent  
on power supply and temperature. The  
monolithic 3D3521 Manchester encoder utilizes  
novel and innovative compensation circuitry to  
minimize timing variations induced by fluctuations  
in power supply and/or temperature.  
RESET  
Power-on reset (Left high for normal operation)  
(RESB)  
1/fC  
1
0
1
1
0
0
1
0
CLOCK  
(CIN)  
tDS  
tDH  
DATA  
(DIN)  
T2H  
T2L  
TRANSMIT  
(TXB)  
T1H  
T1L  
TRANSMIT  
(TX)  
1
0
1
1
0
0
1
0
Figure 1: Timing Diagram  
Doc #06004  
5/8/2006  
DATA DELAY DEVICES, INC.  
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com  
2

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