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3D3220

更新时间： 2024-01-02 05:17:41
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DATADELAY /
页数 文件大小 规格书
4页 240K
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MONOLITHIC 10-TAP FIXED DELAY LINE

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3D3220 数据手册

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3D3220  
MONOLITHIC 10-TAP  
FIXED DELAY LINE  
(SERIES 3D3220)  
FEATURES  
PACKAGES  
•
•
•
•
•
•
•
•
•
•
•
•
All-silicon, low-power CMOS technology  
TTL/CMOS compatible inputs and outputs  
Vapor phase, IR and wave solderable  
Auto-insertable (DIP pkg.)  
IN  
1
2
3
4
5
6
7
14  
VDD  
O1  
IN  
N/C  
O2  
O4  
O6  
VDD  
O1  
O3  
O5  
O7  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
N/C  
O2  
13  
12  
11  
10  
9
O3  
O4  
O5  
O6  
O7  
O8  
O9  
GND  
8
O10  
Low ground bounce noise  
3D3220D-xx SOIC  
Leading- and trailing-edge accuracy  
Delay range: 0.75ns through 7000ns  
Delay tolerance: 2% or 0.5ns  
O8  
GND  
O9  
O10  
IN  
N/C  
N/C  
O2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VDD  
N/C  
O1  
8
Temperature stability: ±2% typical (-40C to 85C)  
Vdd stability: ±1% typical (3.0V-3.6V)  
Minimum input pulse width: 15% of total delay  
14-pin Gull-Wing available as drop-in  
O3  
O4  
O5  
3D3220-xx DIP  
3D3220G-xx Gull-Wing  
O6  
O7  
O8  
O9  
GND  
O10  
For mechanical dimensions, click here.  
For package marking details, click here.  
3D3220S-xx SOL  
replacement for hybrid delay lines  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The 3D3220 10-Tap Delay Line product family consists of fixed-delay  
CMOS integrated circuits. Each package contains a single delay line,  
tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap  
(incremental) delay values can range from 0.75ns through 700ns. The  
input is reproduced at the outputs without inversion, shifted in time as  
per the user-specified dash number. The 3D3220 is TTL- and CMOS-  
compatible, capable of driving ten 74LS-type loads, and features both  
rising- and falling-edge accuracy.  
IN  
Delay Line Input  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
O8  
O9  
Tap 1 Output (10%)  
Tap 2 Output (20%)  
Tap 3 Output (30%)  
Tap 4 Output (40%)  
Tap 5 Output (50%)  
Tap 6 Output (60%)  
Tap 7 Output (70%)  
Tap 8 Output (80%)  
Tap 9 Output (90%)  
The all-CMOS 3D3220 integrated circuit has been designed as a  
reliable, economic alternative to hybrid TTL fixed delay lines. It is  
offered in a standard 14-pin auto-insertable DIP and space saving  
surface mount 14-pin SOIC and 16-pin SOL packages.  
O10 Tap 10 Output (100%)  
VDD +3.3 Volts  
GND Ground  
TABLE 1: PART NUMBER SPECIFICATIONS  
DASH  
TOLERANCES  
INPUT RESTRICTIONS  
NUMBER  
TOTAL  
DELAY (ns)  
6.75 ± 0.5*  
9.0 ± 0.5*  
TAP-TAP  
DELAY (ns)  
0.75 ± 0.4  
1.0 ± 0.5  
1.5 ± 0.7  
2.0 ± 0.8  
2.5 ± 1.0  
4.0 ± 1.3  
5.0 ± 1.5  
10.0 ± 2.0  
20.0 ± 4.0  
50.0 ± 10  
100 ± 20  
700 ± 140  
Rec’d Max  
Frequency  
28.4 MHz  
23.8 MHz  
18.0 MHz  
14.5 MHz  
12.1 MHz  
8.33 MHz  
6.67 MHz  
3.33 MHz  
1.67 MHz  
0.67 MHz  
0.33 MHz  
0.05 MHz  
Absolute Max  
Rec’d Min  
Pulse Width  
17.6 ns  
Absolute Min  
Pulse Width  
3.00 ns  
Frequency  
166.7 MHz  
166.7 MHz  
166.7 MHz  
166.7 MHz  
125.0 MHz  
133.3 MHz  
66.7 MHz  
33.3 MHz  
16.7 MHz  
6.67 MHz  
3.33 MHz  
0.48 MHz  
-.75  
-1  
-1.5  
-2  
-2.5  
-4  
-5  
-10  
-20  
-50  
-100  
-700  
21.0 ns  
3.00 ns  
27.8 ns  
3.00 ns  
13.5 ± 0.5*  
18.0 ± 0.5*  
22.5 ± 0.5*  
36.0 ± 0.7*  
50.0 ± 1.0  
100.0 ± 2.0  
200.0 ± 4.0  
500.0 ± 10  
1000 ± 20  
7000 ± 140  
34.5 ns  
3.00 ns  
41.2 ns  
4.00 ns  
60.0 ns  
6.00 ns  
75.0 ns  
7.50 ns  
150 ns  
15.0 ns  
300 ns  
30.0 ns  
750 ns  
75.0 ns  
1500 ns  
10500 ns  
150 ns  
1050 ns  
* Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns ± 1.0ns  
NOTE: Any dash number between .75 and 700 not shown is also available as standard.  
2005 Data Delay Devices  
Doc #05001  
5/8/2006  
DATA DELAY DEVICES, INC.  
1
3 Mt. Prospect Ave. Clifton, NJ 07013  
1234

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