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37LV128-I/P PDF预览

37LV128-I/P

更新时间: 2024-01-16 05:21:13
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器OTP只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
14页 144K
描述
4K X 32 OTPROM, PDIP8, PLASTIC, DIP-8

37LV128-I/P 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:PLASTIC, DIP-8
针数:8Reach Compliance Code:unknown
风险等级:5.84其他特性:DATA RETENTION >200 YEARS
最大时钟频率 (fCLK):2.5 MHzI/O 类型:COMMON
JESD-30 代码:R-PDIP-T8JESD-609代码:e3
长度:10.033 mm内存密度:131072 bit
内存集成电路类型:OTP ROM功能数量:1
端子数量:8字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4KX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
认证状态:Not Qualified座面最大高度:4.064 mm
最大待机电流:0.00005 A子类别:Other Memory ICs
最大压摆率:0.01 mA最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.6 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mm

37LV128-I/P 数据手册

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37LV36/65/128  
TABLE 11-3: PIN ASSIGNMENTS IN THE PROGRAMMING MODE  
DIP/SOIC  
PLCC Pin  
Name  
DATA  
CLK  
I/O  
I/O  
I
Description  
Pin  
The rising edge of the clock shifts a data word in or out of the  
EPROM one bit at a time.  
1
2
4
2
3
Clock Input. Used to increment the internal address/word  
counter for reading and programming operation.  
6
8
RESET/OE  
I
The rising edge of CLK shifts a data word into the EPROM  
when CE and OE are HIGH; it shifts a data word out of the  
EPROM when CE is LOW and OE is HIGH. The address/  
word counter is incremented on the rising edge of CLK while  
CE is held HIGH and OE is held LOW.  
Note 1: Any modified polarity of the RESET/OE pin is  
ignored in the programming mode.  
4
CE  
I
The rising edge of CLK shifts a data word into the EPROM  
when CE and OE are HIGH; it shifts a data word out of the  
EPROM when CE is LOW and OE is HIGH. The address/  
word counter is incremented on the rising edge of CLK while  
CE is held HIGH and OE is held LOW.  
5
6
10  
14  
VSS  
Ground pin.  
CEO  
O
The polarity of the RESET/OE pin can be read by sensing the  
CEO pin.  
Note 1: The polarity of the RESET/OE pin is ignored while in  
the Programming Mode. In final verification, this pin  
must be monitored to go LOW one clock cycle after  
the last data bit has been read.  
7
8
17  
20  
VPP  
VCC  
Programming Voltage Supply. Programming Mode is entered  
by holding CE and OE HIGH and VPP at VPP1 for two rising  
clock edges and then lowering VPP to VPP2 for one more ris-  
ing clock edge. A word is programmed by strobing the device  
with VPP for the duration TPGM. VPP must be tied to VCC for  
normal read operation.  
+5 V power supply input.  
DS21109F-page 6  
2004 Microchip Technology Inc.  

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