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32C408BRPFE-18 PDF预览

32C408BRPFE-18

更新时间: 2024-02-13 22:23:34
品牌 Logo 应用领域
麦斯威 - MAXWELL 静态存储器内存集成电路
页数 文件大小 规格书
10页 173K
描述
Standard SRAM, 512KX8, 20ns, CMOS, RAD PAK, LDFP-36

32C408BRPFE-18 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:36
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:20 nsJESD-30 代码:R-XDFP-F36
长度:23.622 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端子数量:36
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:512KX8
封装主体材料:UNSPECIFIED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:3.7592 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
总剂量:100k Rad(Si) V宽度:16.383 mm
Base Number Matches:1

32C408BRPFE-18 数据手册

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32C408B  
4 Megabit (512K x 8-Bit) SRAM  
FIGURE 2. TIMING WAVEFORM OF WRITE CYCLE (OE LOW FIXED)  
1. All write cycle timing is referenced from the last valid address to the first transition address.  
2. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and  
WE going low: A write ends at the earliest transition among CS going high or WE going high. tWP is measured from beginning  
of write to end of write.  
3. tCW is measured from the later of CS going low to end of write.  
4. tAS is measured from the address valid to the beginning of write.  
5. tWR is measured from the end of write to the address change. TWR applied in case a write ends as CS or WE going high.  
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase  
of the output must not be applied because bus contention can occur.  
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write  
cycle.  
8. IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.  
9. DOUT is the read data of the new address.  
10.When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be  
applied.  
(1)  
FIGURE 3. TIMING WAVEFORM OF READ CYCLE (ADDRESS CONTROLLED, CS = OE = VIL, WE = VIH)  
1000559  
12.19.01 Rev 6  
All data sheets are subject to change without notice  
6
©2001 Maxwell Technologies  
All rights reserved.  

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