Datasheet > 2EDL05I06BF

2EDL05I06BF

更新时间： 2022-02-26 10:37:15

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
22页	1025K
描述
High voltage gate driver IC

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2EDL05I06BF 数据手册

EiceDRIVER™ Compact

2EDL family

List of Figures

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Typical Application SO8 / SO14 package 0.5 A..................................................................................8

Block diagram for 2EDL05x06Py .........................................................................................................9

Pin Configuration of 2EDL family .......................................................................................................10

Input pin structure...............................................................................................................................11

Input filter timing diagram...................................................................................................................11

Timing of short pulse suppression .....................................................................................................18

Timing of of internal deadtime............................................................................................................18

Input to output propagation delay times and switching times definition.............................................18

Operating areas (IGBT UVLO levels).................................................................................................19

Figure 10 Operating areas (MOSFET UVLO levels)..........................................................................................19

Figure 11 Output pulse width timing and matching delay timing diagram for positive logic...............................19

Figure 12 Package drawing................................................................................................................................20

Figure 13 PCB reference layout left: Reference layout right: detail of footprint..............................................20

Figure 14 Package drawing................................................................................................................................21

Figure 15 PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint....21

Final datasheet

<Revision 2.6>, 01.06.2016

1 2 3 456 7 8...22

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