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2EDF7275KXUMA2 PDF预览

2EDF7275KXUMA2

更新时间: 2024-02-10 08:00:12
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
38页 1488K
描述
MOSFET Driver,

2EDF7275KXUMA2 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:unknownBase Number Matches:1

2EDF7275KXUMA2 数据手册

 浏览型号2EDF7275KXUMA2的Datasheet PDF文件第4页浏览型号2EDF7275KXUMA2的Datasheet PDF文件第5页浏览型号2EDF7275KXUMA2的Datasheet PDF文件第6页浏览型号2EDF7275KXUMA2的Datasheet PDF文件第8页浏览型号2EDF7275KXUMA2的Datasheet PDF文件第9页浏览型号2EDF7275KXUMA2的Datasheet PDF文件第10页 
EiceDRIVER™ 2EDi product family  
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers  
Pin configurations by device type  
For package drawing details see Chapter 7 Package outline dimensions.  
Table 2  
Pin description for dual-channel input mode (with DISABLE, SLDON)  
Pin# Pin# Symbol Description  
DSO LGA  
1
2
INA  
Digital CMOS / TTL logic signal input for channel A with internal pull-down resistor to  
GNDI  
If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4)  
2
3
INB  
Digital CMOS / TTL logic signal input for channel B with internal pull-down resistor to  
GNDI  
If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4)  
3
4
5
7
1
5
VDDI  
GNDI  
Supply voltage (input side) 3.3 V (Internal SLDO available)  
It is recommended to place a bypass capacitor from VDDI to GNDI (see Chapter 3.3.1)  
Ground input side (all signals on input side are referenced to this pin)  
(see Chapter 3.3.1)  
DISABLE Digital CMOS / TTL logic input for both channels A and B; logic input high disables both  
output channels  
Internal pull-down resistor (see Chapter 3.4)  
6
7
8
6
-
N.C.  
Not connected; keep pin floating  
Not connected; keep pin floating  
N.C.  
4
SLDON  
Default 3.3 V supply selected, if N.C. or connected to VDDI  
If SLDON pin is connected to GNDI, SLDO is activated and a supply voltage higher than  
3.5 V can be used (see Chapter 3.3.1)  
Internal pull-up resistor to VDDI; hard-wired PCB connection recommended  
9
8
9
GNDB  
OUTB  
Ground for output channel B  
10  
11  
Output gate driver for channel B  
10 VDDB  
Supply voltage for output channel B  
It is recommended to place a bypass capacitor from VDDB to GNDB (see Chapter 3.3.2)  
12 N.P. N.C.  
Not present; not connected; for channel-to-channel isolation  
Not connected; for channel-to-channel isolation  
Ground for output channel A  
13  
14  
15  
16  
-
N.C.  
11 GNDA  
12 OUTA  
13 VDDA  
Output gate driver for channel A  
Supply voltage for output channel A  
It is recommended to place a bypass capacitor from VDDA to GNDA (see Chapter 3.3.2)  
Final datasheet  
7
Rev.2.5  
2020-03-17  

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