Datasheet > 281GI-XXT

281GI-XXT

更新时间： 2024-02-17 04:25:03

品牌	Logo	应用领域
艾迪悌 - IDT		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
10页	223K
描述
Clock Generator, 200MHz, CMOS, PDSO16, 0.173 INCH, TSSOP-16

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281GI-XXT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	0.173 INCH, TSSOP-16
针数：	16	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.43	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	5 mm
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	200 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	电源：	3.3 V
主时钟/晶体标称频率：	166 MHz	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Clock Generators
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	4.4 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

281GI-XXT 数据手册

ICS281

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER

EPROM CLOCK SYNTHESIZER

The ICS281 also provides separate output divide values,

from 2 through 63, to allow the two output clock banks to

support widely differing frequency values from the same

PLL.

External Components

The ICS281 requires a minimum number of external

components for proper operation.

Each output frequency can be represented as:

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50Ω trace (a commonly

used trace impedance), place a 33Ω resistor in series with

the clock line, as close to the clock output pin as possible.

The nominal impedance of the clock output is 20Ω.

----

OutputFreq = REFFreq ⋅

Output Drive Control

Decoupling Capacitors

The ICS281 has two output drive settings. For VDDO=VDD,

low drive should be selected when outputs are less than 100

MHz. High drive should be selected when outputs are

greater than 100 MHz.

As with any high-performance mixed-signal IC, the ICS281

must be isolated from system power supply noise to perform

optimally.

For VDDO<2.8 V, high drive should be selected for all output

frequencies.

Decoupling capacitors of 0.01µF must be connected

between each VDD and the PCB ground plane. For

optimum device performance, the decoupling capacitor

should be mounted on the component side of the PCB.

Avoid the use of vias on the decoupling circuit.

(Consult the AC Electrical Characteristics for output rise and

fall times for each drive option.)

IDT VersaClock Software

Crystal Load Capacitors

The device crystal connections should include pads for

small capacitors from X1 to ground and from X2 to ground.

These capacitors are used to adjust the stray capacitance of

the board to match the nominally required crystal load

capacitance. Because load capacitance can only be

increased in this trimming process, it is important to keep

stray capacitance to a minimum by using very short PCB

traces (and no vias) between the crystal and device. Crystal

capacitors must be connected from each of the pins X1 and

X2 to ground.

IDT applies years of PLL optimization experience into a user

friendly software that accepts the user’s target reference

clock and output frequencies and generates the lowest jitter,

lowest power configuration, with only a press of a button.

The user does not need to have prior PLL experience or

determine the optimal VCO frequency to support multiple

output frequencies.

VersaClock software quickly evaluates accessible VCO

frequencies with available output divide values and provides

an easy to understand, bar code rating for the target output

frequencies. The user may evaluate output accuracy,

performance trade-off scenarios in seconds.

The value (in pF) of these crystal caps should equal (C -6

pF)*2. In this equation, C = crystal load capacitance in pF.

Example: For a crystal with a 16 pF load capacitance, each

crystal capacitor would be 20 pF [(16-6) x 2 = 20].

Spread Spectrum Modulation

The ICS281 utilizes frequency modulation (FM) to distribute

energy over a range of frequencies. By modulating the

output clock frequencies, the device effectively lowers

energy across a broader range of frequencies; thus,

lowering a system’s electromagnetic interference (EMI). The

modulation rate is the time from transitioning from a

minimum frequency to a maximum frequency and then back

to the minimum.

ICS281 Configuration Capabilities

The architecture of the ICS281 allows the user to easily

configure the device to a wide range of output frequencies,

for a given input reference frequency.

The frequency multiplier PLL provides a high degree of

precision. The M/N values (the multiplier/divide values

available to generate the target VCO frequency) can be set

within the range of M = 1 to 1024 and N = 1 to 32,895.

IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 3

ICS281

REV E 083109

1 234 5 6 7...10

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