Datasheet > 27LC128-15IP

27LC128-15IP

更新时间： 2022-11-25 16:10:42

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器
页数	文件大小	规格书
12页	65K
描述
128K (16K x 8) CMOS EPROM

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27LC128-15IP 数据手册

27C128

FIGURE 1-2: PROGRAMMING WAVEFORMS (1)

Program

Verify

VIH

Address

Data

Address Stable

VIL

V IH

VIL

tAS

t DS

tAH

High Z

Data In Stable

Data Out Valid

tDF

(2)

t DH

13.0 V (3)

5.0 V

6.5 V (3)

5.0 V

VIH

VPP

VCC

tVPS

tVCS

VIL

tCES

V IH

PGM

VIL

tOES

tPW

tOE

(2)

V IH

tOPW

VIL

Notes: (1)

The input timing reference is 0.8V for VIL and 2.0V for VIH.

(2)

(3)

tDF and tOE are characteristics of the device but must be accommodated by the programmer.

Vcc = 6.5V ±0.25V, VPP = VH = 13.0V ±0.25V for Express algorithm.

TABLE 1-6:

MODES

Operation Mode

Read

PGM

VPP

O0 - O7

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VCC

DOUT

DIN

Program

Program Verify

Program Inhibit

Standby

DOUT

High Z

VCC

High Z

Output Disable

Identity

VIH

VIL

VIH

High Z

Identity Code

X = Don’t Care

For Read operations, if the addresses are stable, the

address access time (tACC) is equal to the delay from

CE to output (tCE). Data is transferred to the output

after a delay from the falling edge of OE (tOE).

1.2

Read Mode

(See Timing Diagrams and AC Characteristics)

Read Mode is accessed when

a) the CE pin is low to power up (enable) the chip

b) the OE pin is low to gate the data to the output

pins

1996 Microchip Technology Inc.

DS11003K-page 5

1 2 3 456 7 8...12

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