Datasheet > 276G-XX

276G-XX

更新时间： 2024-01-09 07:51:59

品牌	Logo	应用领域
艾迪悌 - IDT		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
10页	228K
描述
Clock Generator, 200MHz, CMOS, PDSO16, 0.173 INCH, TSSOP-16

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276G-XX 技术参数

生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	0.173 INCH, TSSOP-16	针数：	16
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.73
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	5 mm	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	200 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	主时钟/晶体标称频率：	27 MHz
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	4.4 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

276G-XX 数据手册

ICS276

TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER

EPROM AND VCXO SYNTHESIZER

error =actual initial accuracy (in ppm) of the crystal being

Each output frequency can be represented as:

xtal

measured

----

OutputFreq = REFFreq ⋅

If the centering error is less than 25 ppm, no adjustment is

needed. If the centering error is more than 25 ppm negative,

the PC board has excessive stray capacitance and a new

PCB layout should be considered to reduce stray

capacitance. (Alternately, the crystal may be re-specified to

a higher load capacitance. Contact IDT for details.) If the

centering error is more than 25 ppm positive, add identical

fixed centering capacitors from each crystal pin to ground.

The value for each of these caps (in pF) is given by: External

Capacitor = 2 x (centering error)/(trim sensitivity)

Output Drive Control

The ICS276 has two output drive settings. For VDDO=VDD,

low drive should be selected when outputs are less than 100

MHz. High drive should be selected when outputs are

greater than 100 MHz.

For VDDO<2.8V, high drive should be selected for all output

frequencies.

Trim sensitivity is a parameter which can be supplied by your

crystal vendor. If you do not know the value, assume it is 30

ppm/pF. After any changes, repeat the measurement to

verify that the remaining error is acceptably low (typically

less than 25 ppm).

(Consult the AC Electrical Characteristics for output rise and

fall times for each drive option.)

IDT VersaClock Software

ICS276 Configuration Capabilities

IDT applies years of PLL optimization experience into a user

friendly software that accepts the user’s target reference

clock and output frequencies and generates the lowest jitter,

lowest power configuration, with only a press of a button.

The user does not need to have prior PLL experience or

determine the optimal VCO frequency to support multiple

output frequencies.

The architecture of the ICS276 allows the user to easily

configure the device to a wide range of output frequencies,

for a given input reference frequency.

The frequency multiplier PLL provides a high degree of

precision. The M/N values (the multiplier/divide values

available to generate the target VCO frequency) can be set

within the range of M = 1 to 1024 and N = 1 to 32,895.

VersaClock software quickly evaluates accessible VCO

frequencies with available output divide values and provides

an easy to understand, bar code rating for the target output

frequencies. The user may evaluate output accuracy,

performance trade-off scenarios in seconds.

The ICS276 also provides separate output divide values,

from 2 through 63, to allow the two output clock banks to

support widely differing frequency values from the same

PLL.

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS276. These ratings, which are

standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these

or any other conditions above those indicated in the operational sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical

parameters are guaranteed only over the recommended operating temperature range.

Parameter

Condition

Min.

Typ.

Max.

Units

Supply Voltage, VDD

Inputs

Referenced to GND

-0.5

VDD+0.5

Clock Outputs

IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 4

ICS276

REV D 081809

1 2 345 6 7...10

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与276G-XX相关器件

型号	品牌	描述	获取价格	数据表
276G-XXLF	IDT	Clock Generator, 200MHz, CMOS, PDSO16, 0.173 INCH, ROHS COMPLIANT, TSSOP-16	获取价格
276G-XXLFT	IDT	Clock Generator, 200MHz, CMOS, PDSO16, 0.173 INCH, ROHS COMPLIANT, TSSOP-16	获取价格
276G-XXT	IDT	Clock Generator, 200MHz, CMOS, PDSO16, 0.173 INCH, TSSOP-16	获取价格
276HC5550KR	CDE	300 μΩ	获取价格
276KFM160MGBW	ILLINOISCAPACITOR	High temperature - High voltage â Long Life	获取价格
276KFM160MGBW	CDE	410 mA @ 100 kHz, 105°C	获取价格

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