ICS275
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER
EPROM VCXO AND SYNTHESIZER
error =actual initial accuracy (in ppm) of the crystal being
measured
The ICS275 also provides separate output divide values,
from 2 through 63, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
xtal
If the centering error is less than 25 ppm, no adjustment is
needed. If the centering error is more than 25ppm negative,
the PC board has excessive stray capacitance and a new
PCB layout should be considered to reduce stray
capacitance. (Alternately, the crystal may be re-specified to
a higher load capacitance. Contact IDT for details.) If the
centering error is more than 25 ppm positive, add identical
fixed centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by: External
Capacitor = 2 x (centering error)/(trim sensitivity)
Each output frequency can be represented as:
M
N
----
OutputFreq = REFFreq ⋅
IDT VersaClock Software
IDT applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
Trim sensitivity is a parameter which can be supplied by your
crystal vendor. If you do not know the value, assume it is 30
ppm/pF. After any changes, repeat the measurement to
verify that the remaining error is acceptably low (typically
less than 25 ppm).
ICS275 Configuration Capabilities
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
The architecture of the ICS275 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 1024 and N = 1 to 32,895.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS275. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Condition
Min.
Typ.
Max.
7
Units
V
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
VDD+0.5
VDD+0.5
150
V
Clock Outputs
V
Storage Temperature
Soldering Temperature
Junction Temperature
°C
°C
°C
Max 10 seconds
260
125
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 4
ICS275
REV D 102808
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