25CSM04
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
TA = -40°C to +85°C
VCC = 2.5V to 5.5V
Param.
Symbol
No.
Characteristic
Clock Frequency
CS Setup Time
Min.
Max.
Units
Test Conditions
1
2
3
4
5
6
FCLK
—
—
30
60
30
60
30
60
10
20
10
20
50
50
40
80
40
80
50
50
—
—
0
8
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
VCC ≥ 3.0V
VCC ≥ 2.5V
5
TCSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
40
80
—
40
80
—
—
—
—
—
—
—
—
5
VCC ≥ 3.0V
VCC ≥ 2.5V
VCC ≥ 3.0V
VCC ≥ 2.5V
VCC ≥ 3.0V
VCC ≥ 2.5V
VCC ≥ 3.0V
VCC ≥ 2.5V
VCC ≥ 3.0V
VCC ≥ 2.5V
Note 1
TCSH CS Hold Time
TCSD CS Disable Time
TSU
THD
Data Setup Time
Data Hold Time
7
8
9
TR
TF
CLK Rise Time
CLK Fall Time
Clock High Time
Note 1
THI
VCC ≥ 3.0V
VCC ≥ 2.5V
VCC ≥ 3.0V
VCC ≥ 2.5V
10
TLO
Clock Low Time
11
12
13
TCLD
TCLE
TV
Clock Delay Time
Clock Enable Time
Output Valid from Clock Low
VCC ≥ 3.0V
VCC ≥ 2.5V
Note 1
14
15
THO
TDIS
Output Hold Time
Output Disable Time
—
—
10
20
10
20
40
80
40
80
—
VCC ≥ 3.0V
VCC ≥ 2.5V
VCC ≥ 3.0V
VCC ≥ 2.5V
VCC ≥ 3.0V
VCC ≥ 2.5V
VCC ≥ 3.0V (Note 1)
VCC ≥ 2.5V (Note 1)
VCC ≥ 3.0V
VCC ≥ 2.5V
Note 2
16
17
18
19
20
THS
THH
THZ
THV
TWC
HOLD Setup Time
HOLD Hold Time
HOLD Low to Output High Z
HOLD High to Output Valid
Internal Write Cycle Time
Note 1: This parameter is not tested but ensured by characterization.
2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is
complete.
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DS20005817C-page 5