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24LC64T-/ST PDF预览

24LC64T-/ST

更新时间： 2024-01-01 13:57:55
品牌 Logo 应用领域
其他 - ETC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 169K
描述
I2C Serial EEPROM

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24LC64T-/ST 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51Factory Lead Time：6 weeks
风险等级：1.02Is Samacsys：N
其他特性：DATA RETENTION > 200 YEARS; 1000000 ERASE/WRITE CYCLES GUARANTEED最大时钟频率 (fCLK)：0.4 MHz
数据保留时间-最小值：200耐久性：1000000 Write/Erase Cycles
I2C控制字节：1010DDDRJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.4 mm
内存密度：65536 bit内存集成电路类型：EEPROM
内存宽度：8湿度敏感等级：1
功能数量：1端子数量：8
字数：8192 words字数代码：8000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：8KX8
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行：SERIAL
峰值回流温度（摄氏度）：260电源：2/5 V
认证状态：Not Qualified座面最大高度：1.1 mm
串行总线类型：I2C最大待机电流：0.000001 A
子类别：EEPROMs最大压摆率：0.003 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：3 mm
最长写入周期时间 (tWC)：5 ms写保护：HARDWARE
Base Number Matches：1

24LC64T-/ST 数据手册

 浏览型号24LC64T-/ST的Datasheet PDF文件第4页浏览型号24LC64T-/ST的Datasheet PDF文件第5页浏览型号24LC64T-/ST的Datasheet PDF文件第6页浏览型号24LC64T-/ST的Datasheet PDF文件第8页浏览型号24LC64T-/ST的Datasheet PDF文件第9页浏览型号24LC64T-/ST的Datasheet PDF文件第10页 
24AA64/24LC64  
6.2  
Page Write  
6.0  
WRITE OPERATIONS  
The write control byte, word address and the first data  
byte are transmitted to the 24xx64 in the same way as  
in a byte write. But instead of generating a stop condi-  
tion, the master transmits up to 31 additional bytes  
which are temporarily stored in the on-chip page buffer  
and will be written into memory after the master has  
transmitted a stop condition. After receipt of each word,  
the five lower address pointer bits are internally incre-  
mented by one. If the master should transmit more than  
32 bytes prior to generating the stop condition, the  
address counter will roll over and the previously  
received data will be overwritten. As with the byte write  
operation, once the stop condition is received, an inter-  
nal write cycle will begin (Figure 6-2). If an attempt is  
made to write to the array with the WP pin held high, the  
device will acknowledge the command but no write  
cycle will occur, no data will be written and the device  
will immediately accept a new command.  
6.1  
Byte Write  
Following the start condition from the master, the  
control code (four bits), the chip select (three bits), and  
the R/W bit (which is a logic low) are clocked onto the  
bus by the master transmitter. This indicates to the  
addressed slave receiver that the address high byte will  
follow after it has generated an acknowledge bit during  
the ninth clock cycle. Therefore, the next byte transmit-  
ted by the master is the high-order byte of the word  
address and will be written into the address pointer of  
the 24xx64. The next byte is the least significant  
address byte. After receiving another acknowledge sig-  
nal from the 24xx64 the master device will transmit the  
data word to be written into the addressed memory  
location. The 24xx64 acknowledges again and the  
master generates a stop condition. This initiates the  
internal write cycle, and during this time the 24xx64 will  
not generate acknowledge signals (Figure 6-1). If an  
attempt is made to write to the array with the WP pin  
held high, the device will acknowledge the command  
but no write cycle will occur, no data will be written and  
the device will immediately accept a new command.  
After a byte write command, the internal address  
counter will point to the address location following the  
one that was just written.  
6.3  
Write Protection  
The WP pin allows the user to write protect the entire  
array (0000-1FFF) when the pin is tied to Vcc. If tied to  
VSS or left floating, the write protection is disabled. The  
WP pin is sampled at the STOP bit for every write com-  
mand (Figure 1-1) Toggling the WP pin after the STOP  
bit will have no effect on the execution of the write cycle.  
FIGURE 6-1: BYTE WRITE  
S
BUS ACTIVITY  
T
S
T
O
P
CONTROL  
BYTE  
ADDRESS  
HIGH BYTE  
ADDRESS  
LOW BYTE  
MASTER  
A
R
T
DATA  
A A A  
2 1 0  
SDA LINE  
X X X  
S 1 0 1 0  
0
P
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY  
X = don’t care bit  
FIGURE 6-2: PAGE WRITE  
S
T
A
R
T
S
T
O
P
CONTROL  
BYTE  
ADDRESS  
HIGH BYTE  
ADDRESS  
LOW BYTE  
BUS ACTIVITY  
MASTER  
DATA BYTE 0  
DATA BYTE 31  
A A A  
2 1 0  
SDA LINE  
X X X  
P
S 1 0 1 0  
0
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY  
X = don’t care bit  
2000 Microchip Technology Inc.  
DS21189D-page 7  
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