Datasheet > 24LC64T-/ST

24LC64T-/ST

更新时间： 2024-02-11 02:27:23

品牌	Logo	应用领域
其他 - ETC		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
12页	169K
描述
I2C Serial EEPROM

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24LC64T-/ST 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	Factory Lead Time：	6 weeks
风险等级：	1.02	Is Samacsys：	N
其他特性：	DATA RETENTION > 200 YEARS; 1000000 ERASE/WRITE CYCLES GUARANTEED	最大时钟频率 (fCLK)：	0.4 MHz
数据保留时间-最小值：	200	耐久性：	1000000 Write/Erase Cycles
I2C控制字节：	1010DDDR	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.4 mm
内存密度：	65536 bit	内存集成电路类型：	EEPROM
内存宽度：	8	湿度敏感等级：	1
功能数量：	1	端子数量：	8
字数：	8192 words	字数代码：	8000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	8KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260	电源：	2/5 V
认证状态：	Not Qualified	座面最大高度：	1.1 mm
串行总线类型：	I2C	最大待机电流：	0.000001 A
子类别：	EEPROMs	最大压摆率：	0.003 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	3 mm
最长写入周期时间 (tWC)：	5 ms	写保护：	HARDWARE
Base Number Matches：	1

24LC64T-/ST 数据手册

24AA64/24LC64

2.0

PIN DESCRIPTIONS

4.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

2.1

A0, A1, A2 Chip Address Inputs

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

The A0,A1,A2 inputs are used by the 24xx64 for multi-

ple device operation. The levels on these inputs are

compared with the corresponding bits in the slave

address. The chip is selected if the compare is true.

Up to eight devices may be connected to the same bus

by using different chip select bit combinations. These

inputs must be connected to either VCC or VSS.

Accordingly, the following bus conditions have been

defined (Figure 4-1).

2.2

SDA Serial Data

4.1

Bus not Busy (A)

This is a bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open-

drain terminal, therefore, the SDA bus requires a pullup

resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for

400 kHz)

Both data and clock lines remain HIGH.

4.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

4.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must end with a STOP condition.

2.3

SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

4.4

Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

2.4

This pin can be connected to either Vss, Vcc or left

floating. An internal pull-down resistor on this pin will

keep the device in the unprotected state if left floating.

If tied to Vss or left floating, normal memory operation

is enabled (read/write the entire memory 0000-1FFF).

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device.

If tied to VCC, WRITE operations are inhibited. Read

operations are not affected.

3.0

FUNCTIONAL DESCRIPTION

4.5

Acknowledge

The 24xx64 supports a bi-directional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, and a device

receiving data as a receiver. The bus must be con-

trolled by a master device which generates the serial

clock (SCL), controls the bus access, and generates

the START and STOP conditions while the 24xx64

works as a slave. Both master and slave can operate as

a transmitter or receiver but the master device deter-

mines which mode is activated.

Each receiving device, when addressed, is obliged to

generate an acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this acknowledge

bit.

Note: The 24xx64 does not generate any

acknowledge bits if an internal program-

ming cycle is in progress.

A device that acknowledges must pull down the SDA

line during the acknowledge clock pulse in such a way

that the SDA line is stable LOW during the HIGH period

of the acknowledge related clock pulse. Of course,

setup and hold times must be taken into account. Dur-

ing reads, a master must signal an end of data to the

slave by NOT generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this case,

the slave (24xx64) will leave the data line HIGH to

enable the master to generate the STOP condition.

DS21189D-page 4

2000 Microchip Technology Inc.

1 2 345 6 7...12

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