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24LC320-SN

更新时间: 2022-11-28 20:37:17
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 90K
描述
32K 2.5V SPI Bus Serial EEPROM

24LC320-SN 数据手册

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25LC320  
2.2  
Read Status Register (RDSR)  
2.0  
PRINCIPLES OF OPERATION  
The 25LC320 is a 4096 byte EEPROM designed to  
interface directly with the serial peripheral interface  
(SPI ) port of many of today’s popular microcontroller  
families, including Microchip’s midrange PIC16CXX  
microcontrollers. It may also interface with microcontrol-  
lers that do not have a built-in SPI port by using dis-  
crete I/O lines programmed properly with software.  
The RDSR instruction provides access to the status  
register. The status register may be read at any time,  
even during a write cycle. The status register is format-  
ted as follows:  
7
6
5
4
3
2
1
0
WPEN  
X
X
X
BP1  
BP0  
WEL  
WIP  
The Write-In-Process (WIP) bit indicates whether the  
25LC320 is busy with a write operation. When set to a  
‘1’ a write is in progress, when set to a ‘0’ no write is in  
progress. This bit is read only.  
The 25LC320 contains an 8-bit instruction register.The  
part is accessed via the SI pin, with data being clocked  
in on the rising edge of SCK. If the WPEN bit in the Sta-  
tus Register is set, the WP pin must be held high to  
allow writing to the non-volatile bits in the status regis-  
ter.  
The Write Enable Latch (WEL) bit indicates the status  
of the write enable latch. When set to a ‘1’ the latch  
allows writes to the array and status register, when set  
to a ‘0’ the latch prohibits writes to the array and status  
register. The state of this bit can always be updated via  
the WREN or WRDI commands regardless of the state  
of write protection on the status register.This bit is read  
only.  
Table 2-1 contains a list of the possible instruction bytes  
and format for device operation. All instructions,  
addresses and data are transferred MSB first, LSB last.  
Data is sampled on the first rising edge of SCK after CS  
goes low. If the clock line is shared with other peripheral  
devices on the SPI bus, the user can assert the  
HOLD input and place the 25LC320 in ‘HOLD’ mode.  
After releasing the HOLD pin, operation will resume  
from the point when the HOLD was asserted.  
The Block Protection (BP0 and BP1) bits indicate  
which blocks are currently write protected. These bits  
are set by the user issuing the WRSR instruction.  
These bits are non-volatile.  
2.1  
Write Enable (WREN) and Write  
Disable (WRDI)  
The Write Protect Enable (WPEN) bit is a non-volatile  
bit that is available as an enable bit for the WP pin. The  
Write Protect (WP) pin and the Write Protect Enable  
(WPEN) bit in the status register control the  
programmable hardware write protect feature.  
Hardware write protection is enabled when WP pin is  
low and the WPEN bit is high. Hardware write  
protection is disabled when either the WP pin is high or  
the WPEN bit is low. When the chip is hardware write  
protected, only writes to non-volatile bits in the status  
register are disabled. See Table 2-2 for matrix of  
functionality on the WPEN bit and Figure 2-1 for a  
flowchart of Table 2-2. See Figure 3-5 for RDSR timing  
sequence.  
The 25LC320 contains a write enable latch. This latch  
must be set before any write operation will be  
completed internally. The WREN instruction will set the  
latch, and the WRDI will reset the latch.The following is  
a list of conditions under which the write enable latch  
will be reset:  
• Power-up  
• WRDI instruction successfully executed  
• WRSR instruction successfully executed  
• WRITE instruction successfully executed  
TABLE 2-1:  
INSTRUCTION SET  
Instruction Name Instruction Format  
Description  
WREN  
WRDI  
RDSR  
WRSR  
READ  
WRITE  
0000 0110  
0000 0100  
0000 0101  
0000 0001  
0000 0011  
0000 0010  
Set the write enable latch (enable write operations)  
Reset the write enable latch (disable write operations)  
Read status register  
Write status register (write protect enable and block write protection bits)  
Read data from memory array beginning at selected address  
Write data to memory array beginning at selected address  
TABLE 2-2:  
WRITE PROTECT FUNCTIONALITY MATRIX  
WPEN  
WP  
WEL  
Protected Blocks  
Unprotected Blocks  
Status Register  
0
0
1
1
X
X
X
X
Low  
Low  
High  
High  
0
1
0
1
0
1
Protected  
Protected  
Protected  
Protected  
Protected  
Protected  
Protected  
Writable  
Protected  
Writable  
Protected  
Writable  
Protected  
Writable  
Protected  
Protected  
Protected  
Writable  
1996 Microchip Technology Inc.  
Preliminary  
DS21158B-page 5  

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