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24LC04B-/P PDF预览

24LC04B-/P

更新时间： 2024-02-16 20:17:09
品牌 Logo 应用领域
其他 - ETC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 163K
描述
I2C Serial EEPROM

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24LC04B-/P 技术参数

是否Rohs认证： 不符合生命周期：Active
Reach Compliance Code：unknown风险等级：5.53
数据保留时间-最小值：100耐久性：100000 Write/Erase Cycles
I2C控制字节：1010DDMRJESD-30 代码：R-PDSO-G14
JESD-609代码：e0内存密度：4096 bit
内存集成电路类型：EEPROM内存宽度：8
端子数量：14字数：512 words
字数代码：512最高工作温度：85 °C
最低工作温度：-40 °C组织：512X8
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：SERIAL
电源：3/5 V认证状态：Not Qualified
串行总线类型：I2C最大待机电流：0.00003 A
子类别：EEPROMs最大压摆率：0.003 mA
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL写保护：HARDWARE
Base Number Matches：1

24LC04B-/P 数据手册

 浏览型号24LC04B-/P的Datasheet PDF文件第3页浏览型号24LC04B-/P的Datasheet PDF文件第4页浏览型号24LC04B-/P的Datasheet PDF文件第5页浏览型号24LC04B-/P的Datasheet PDF文件第7页浏览型号24LC04B-/P的Datasheet PDF文件第8页浏览型号24LC04B-/P的Datasheet PDF文件第9页 
24LC04B/08B  
after the master has transmitted a stop condition. After  
the receipt of each word, the four lower order address  
pointer bits are internally incremented by one. The  
higher order seven bits of the word address remains  
constant. If the master should transmit more than 16  
words prior to generating the stop condition, the  
address counter will roll over and the previously  
received data will be overwritten. As with the byte write  
operation, once the stop condition is received an inter-  
nal write cycle will begin (Figure 4-2).  
4.0  
WRITE OPERATION  
4.1  
Byte Write  
Following the start condition from the master, the  
device code (4 bits), the block address (3 bits), and the  
R/W bit which is a logic low is placed onto the bus by  
the master transmitter. This indicates to the addressed  
slave receiver that a byte with a word address will follow  
after it has generated an acknowledge bit during the  
ninth clock cycle. Therefore the next byte transmitted  
by the master is the word address and will be written  
into the address pointer of the 24LC04B/08B. After  
receiving another acknowledge signal from the  
24LC04B/08B the master device will transmit the data  
word to be written into the addressed memory location.  
The 24LC04B/08B acknowledges again and the mas-  
ter generates a stop condition. This initiates the inter-  
nal write cycle, and during this time the 24LC04B/08B  
will not generate acknowledge signals (Figure 4-1).  
Note: Page write operations are limited to writing  
bytes within a single physical page, regard-  
less of the number of bytes actually being  
written. Physical page boundaries start at  
addresses that are integer multiples of the  
page buffer size (or Ôpage sizeÕ) and end at  
addresses that are integer multiples of  
[page size - 1]. If a page write command  
attempts to write across a physical page  
boundary, the result is that the data wraps  
around to the beginning of the current page  
(overwriting data previously stored there),  
instead of being written to the next page as  
might be expected. It is therefore neces-  
sary for the application software to prevent  
page write operations that would attempt to  
cross a page boundary.  
4.2  
Page Write  
The write control byte, word address and the first data  
byte are transmitted to the 24LC04B/08B in the same  
way as in a byte write. But instead of generating a stop  
condition the master transmits up to 16 data bytes to  
the 24LC04B/08B which are temporarily stored in the  
on-chip page buffer and will be written into the memory  
FIGURE 4-1: BYTE WRITE  
S
T
A
R
T
S
BUS ACTIVITY  
MASTER  
CONTROL  
BYTE  
WORD  
ADDRESS  
T
DATA  
O
P
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY  
FIGURE 4-2: PAGE WRITE  
S
BUS ACTIVITY  
MASTER  
T
A
R
T
S
T
O
P
CONTROL  
BYTE  
WORD  
ADDRESS (n)  
DATA n  
DATA n + 1  
DATA n + 15  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY  
DS21051G-page 6  
1999 Microchip Technology Inc.  
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